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Results 1 - 1 of 1 for T4 (0.02 sec)

  1. src/cmd/asm/internal/arch/arch.go

    	register["S7"] = riscv.REG_S7
    	register["S8"] = riscv.REG_S8
    	register["S9"] = riscv.REG_S9
    	register["S10"] = riscv.REG_S10
    	// Skip S11 as it is the g register.
    	register["T3"] = riscv.REG_T3
    	register["T4"] = riscv.REG_T4
    	register["T5"] = riscv.REG_T5
    	register["T6"] = riscv.REG_T6
    
    	// Go runtime register names.
    	register["g"] = riscv.REG_G
    	register["CTXT"] = riscv.REG_CTXT
    	register["TMP"] = riscv.REG_TMP
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Thu Oct 24 12:32:56 UTC 2024
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