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Results 1 - 4 of 4 for T3 (0.05 sec)

  1. src/test/java/org/codelibs/core/lang/GenericsUtilTest.java

            final Method m3 = MapType.class.getMethod("mapOfWildcard");
            final Type t3 = m3.getGenericReturnType();
            assertThat(GenericsUtil.isTypeOf(t3, Map.class), is(true));
            assertThat(WildcardType.class.isInstance(GenericsUtil.getKeyTypeOfMap(t3)), is(true));
            assertThat(WildcardType.class.isInstance(GenericsUtil.getValueTypeOfMap(t3)), is(true));
        }
    
        /**
         * @throws Exception
         */
    Registered: Fri Nov 01 20:58:10 UTC 2024
    - Last Modified: Thu Mar 07 01:59:08 UTC 2024
    - 11.5K bytes
    - Viewed (0)
  2. android/guava/src/com/google/common/util/concurrent/RateLimiter.java

         * all calling acquire() at these moments:
         *
         * T0 at 0 seconds
         * T1 at 1.05 seconds
         * T2 at 2 seconds
         * T3 at 3 seconds
         *
         * Due to the slight delay of T1, T2 would have to sleep till 2.05 seconds, and T3 would also
         * have to sleep till 3.05 seconds.
         */
        return create(permitsPerSecond, SleepingStopwatch.createFromSystemTimer());
      }
    
    Registered: Fri Nov 01 12:43:10 UTC 2024
    - Last Modified: Sat Oct 19 00:51:36 UTC 2024
    - 21.9K bytes
    - Viewed (0)
  3. guava/src/com/google/common/util/concurrent/RateLimiter.java

         * all calling acquire() at these moments:
         *
         * T0 at 0 seconds
         * T1 at 1.05 seconds
         * T2 at 2 seconds
         * T3 at 3 seconds
         *
         * Due to the slight delay of T1, T2 would have to sleep till 2.05 seconds, and T3 would also
         * have to sleep till 3.05 seconds.
         */
        return create(permitsPerSecond, SleepingStopwatch.createFromSystemTimer());
      }
    
    Registered: Fri Nov 01 12:43:10 UTC 2024
    - Last Modified: Sat Oct 19 00:51:36 UTC 2024
    - 21.6K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/arch/arch.go

    	register["S6"] = riscv.REG_S6
    	register["S7"] = riscv.REG_S7
    	register["S8"] = riscv.REG_S8
    	register["S9"] = riscv.REG_S9
    	register["S10"] = riscv.REG_S10
    	// Skip S11 as it is the g register.
    	register["T3"] = riscv.REG_T3
    	register["T4"] = riscv.REG_T4
    	register["T5"] = riscv.REG_T5
    	register["T6"] = riscv.REG_T6
    
    	// Go runtime register names.
    	register["g"] = riscv.REG_G
    	register["CTXT"] = riscv.REG_CTXT
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Thu Oct 24 12:32:56 UTC 2024
    - 21.5K bytes
    - Viewed (0)
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