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Results 1 - 10 of 16 for SRL (0.04 sec)

  1. test/codegen/shift.go

    	return v >> uint64(33)
    }
    
    func rshConst64Ux64Overflow32(v uint32) uint64 {
    	// riscv64:"MOV\t\\$0,",-"SRL"
    	return uint64(v) >> 32
    }
    
    func rshConst64Ux64Overflow16(v uint16) uint64 {
    	// riscv64:"MOV\t\\$0,",-"SRL"
    	return uint64(v) >> 16
    }
    
    func rshConst64Ux64Overflow8(v uint8) uint64 {
    	// riscv64:"MOV\t\\$0,",-"SRL"
    	return uint64(v) >> 8
    }
    
    func rshConst64x64(v int64) int64 {
    	// ppc64x:"SRAD"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 21 18:53:43 UTC 2024
    - 12.7K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (Rsh8Ux32  <t> x y) && !shiftIsBounded(v) => (AND (SRL  <t> (ZeroExt8to64  x) y) (Neg8  <t> (SLTIU <t> [64] (ZeroExt32to64 y))))
    (Rsh8Ux64  <t> x y) && !shiftIsBounded(v) => (AND (SRL  <t> (ZeroExt8to64  x) y) (Neg8  <t> (SLTIU <t> [64] y)))
    (Rsh16Ux8  <t> x y) && !shiftIsBounded(v) => (AND (SRL  <t> (ZeroExt16to64 x) y) (Neg16 <t> (SLTIU <t> [64] (ZeroExt8to64  y))))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/mips64.s

    	SLLV	R10, R22, R21	// 0156a814
    	SRL	R27, R6, R17	// 03668806
    	SRLV	R27, R6, R17	// 03668816
    	SRA	R11, R19, R20	// 0173a007
    	SRAV	R20, R19, R19	// 02939817
    	ROTR	R19, R18, R20	// 0272a046
    	ROTRV	R9, R13, R16	// 012d8056
    
    //	LSHW rreg ',' rreg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	SLL	R1, R2		// 00221004
    	SLLV	R10, R22	// 0156b014
    	SRL	R27, R6   	// 03663006
    	SRLV	R27, R6   	// 03663016
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 12.4K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/MIPS.rules

    (Rsh32Ux32 <t> x y) => (CMOVZ (SRL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
    (Rsh32Ux16 <t> x y) => (CMOVZ (SRL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
    (Rsh32Ux8 <t> x y)  => (CMOVZ (SRL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
    
    (Rsh16Ux32 <t> x y) => (CMOVZ (SRL <t> (ZeroExt16to32 x) y) (MOVWconst [0]) (SGTUconst [32] y))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 35.3K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/riscv64.s

    	LUI	$524287, X15				// b7f7ff7f
    
    	SLL	X6, X5, X7				// b3936200
    	SLL	X5, X6					// 33135300
    	SLL	$1, X5, X6				// 13931200
    	SLL	$1, X5					// 93921200
    	SRL	X6, X5, X7				// b3d36200
    	SRL	X5, X6					// 33535300
    	SRL	$1, X5, X6				// 13d31200
    	SRL	$1, X5					// 93d21200
    
    	SUB	X6, X5, X7				// b3836240
    	SUB	X5, X6					// 33035340
    	SUB	$-2047, X5, X6				// 1383f27f
    	SUB	$2048, X5, X6				// 13830280
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 22 04:42:21 UTC 2024
    - 16.7K bytes
    - Viewed (0)
  6. test/codegen/arithmetic.go

    func LenDiv1(a []int) int {
    	// 386:"SHRL\t[$]10"
    	// amd64:"SHRQ\t[$]10"
    	// arm64:"LSR\t[$]10",-"SDIV"
    	// arm:"SRL\t[$]10",-".*udiv"
    	// ppc64x:"SRD"\t[$]10"
    	return len(a) / 1024
    }
    
    func LenDiv2(s string) int {
    	// 386:"SHRL\t[$]11"
    	// amd64:"SHRQ\t[$]11"
    	// arm64:"LSR\t[$]11",-"SDIV"
    	// arm:"SRL\t[$]11",-".*udiv"
    	// ppc64x:"SRD\t[$]11"
    	return len(s) / (4097 >> 1)
    }
    
    func LenMod1(a []int) int {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 15:28:00 UTC 2024
    - 15.2K bytes
    - Viewed (0)
  7. src/main/java/org/codelibs/fess/es/log/allcommon/EsAbstractConditionQuery.java

    import org.dbflute.dbmeta.info.ColumnInfo;
    import org.dbflute.dbmeta.name.ColumnRealName;
    import org.dbflute.dbmeta.name.ColumnSqlName;
    import org.dbflute.exception.InvalidQueryRegisteredException;
    import org.dbflute.util.Srl;
    import org.opensearch.common.unit.Fuzziness;
    import org.opensearch.index.query.BoolQueryBuilder;
    import org.opensearch.index.query.CommonTermsQueryBuilder;
    import org.opensearch.index.query.ExistsQueryBuilder;
    Registered: Wed Jun 12 13:08:18 UTC 2024
    - Last Modified: Thu Feb 22 01:37:57 UTC 2024
    - 21.1K bytes
    - Viewed (0)
  8. src/main/java/org/codelibs/fess/es/config/allcommon/EsAbstractConditionQuery.java

    import org.dbflute.dbmeta.info.ColumnInfo;
    import org.dbflute.dbmeta.name.ColumnRealName;
    import org.dbflute.dbmeta.name.ColumnSqlName;
    import org.dbflute.exception.InvalidQueryRegisteredException;
    import org.dbflute.util.Srl;
    import org.opensearch.common.unit.Fuzziness;
    import org.opensearch.index.query.BoolQueryBuilder;
    import org.opensearch.index.query.CommonTermsQueryBuilder;
    import org.opensearch.index.query.ExistsQueryBuilder;
    Registered: Wed Jun 12 13:08:18 UTC 2024
    - Last Modified: Thu Feb 22 01:37:57 UTC 2024
    - 21.1K bytes
    - Viewed (0)
  9. src/main/java/org/codelibs/fess/es/user/allcommon/EsAbstractConditionQuery.java

    import org.dbflute.dbmeta.info.ColumnInfo;
    import org.dbflute.dbmeta.name.ColumnRealName;
    import org.dbflute.dbmeta.name.ColumnSqlName;
    import org.dbflute.exception.InvalidQueryRegisteredException;
    import org.dbflute.util.Srl;
    import org.opensearch.common.unit.Fuzziness;
    import org.opensearch.index.query.BoolQueryBuilder;
    import org.opensearch.index.query.CommonTermsQueryBuilder;
    import org.opensearch.index.query.ExistsQueryBuilder;
    Registered: Wed Jun 12 13:08:18 UTC 2024
    - Last Modified: Thu Feb 22 01:37:57 UTC 2024
    - 21.1K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/_gen/MIPSOps.go

    		{name: "SLLconst", argLength: 1, reg: gp11, asm: "SLL", aux: "Int32"}, // arg0 << auxInt, shift amount must be 0 through 31 inclusive
    		{name: "SRL", argLength: 2, reg: gp21, asm: "SRL"},                    // arg0 >> arg1, unsigned, shift amount is mod 32
    		{name: "SRLconst", argLength: 1, reg: gp11, asm: "SRL", aux: "Int32"}, // arg0 >> auxInt, shift amount must be 0 through 31 inclusive
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 24K bytes
    - Viewed (0)
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