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Results 1 - 6 of 6 for ROTR (0.03 sec)

  1. src/cmd/internal/notsha256/sha256block_amd64.s

    #define MSGSCHEDULE0(index) \
    	MOVL	(index*4)(SI), AX; \
    	BSWAPL	AX; \
    	MOVL	AX, (index*4)(BP)
    
    // Wt = SIGMA1(Wt-2) + Wt-7 + SIGMA0(Wt-15) + Wt-16; for 16 <= t <= 63
    //   SIGMA0(x) = ROTR(7,x) XOR ROTR(18,x) XOR SHR(3,x)
    //   SIGMA1(x) = ROTR(17,x) XOR ROTR(19,x) XOR SHR(10,x)
    #define MSGSCHEDULE1(index) \
    	MOVL	((index-2)*4)(BP), AX; \
    	MOVL	AX, CX; \
    	RORL	$17, AX; \
    	MOVL	CX, DX; \
    	RORL	$19, CX; \
    	SHRL	$10, DX; \
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 19 23:33:27 UTC 2023
    - 14K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/mips64.s

    	SRAV	R20, R19, R19	// 02939817
    	ROTR	R19, R18, R20	// 0272a046
    	ROTRV	R9, R13, R16	// 012d8056
    
    //	LSHW rreg ',' rreg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	SLL	R1, R2		// 00221004
    	SLLV	R10, R22	// 0156b014
    	SRL	R27, R6   	// 03663006
    	SRLV	R27, R6   	// 03663016
    	SRA	R11, R19	// 01739807
    	SRAV	R20, R19	// 02939817
    	ROTR	R20, R19	// 02939846
    	ROTRV	R16, R9		// 02094856
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 12.4K bytes
    - Viewed (0)
  3. src/crypto/sha256/sha256block_amd64.s

    #define MSGSCHEDULE0(index) \
    	MOVL	(index*4)(SI), AX; \
    	BSWAPL	AX; \
    	MOVL	AX, (index*4)(BP)
    
    // Wt = SIGMA1(Wt-2) + Wt-7 + SIGMA0(Wt-15) + Wt-16; for 16 <= t <= 63
    //   SIGMA0(x) = ROTR(7,x) XOR ROTR(18,x) XOR SHR(3,x)
    //   SIGMA1(x) = ROTR(17,x) XOR ROTR(19,x) XOR SHR(10,x)
    #define MSGSCHEDULE1(index) \
    	MOVL	((index-2)*4)(BP), AX; \
    	MOVL	AX, CX; \
    	RORL	$17, AX; \
    	MOVL	CX, DX; \
    	RORL	$19, CX; \
    	SHRL	$10, DX; \
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 47.3K bytes
    - Viewed (0)
  4. src/crypto/sha512/sha512block_amd64.s

    #define MSGSCHEDULE0(index) \
    	MOVQ	(index*8)(SI), AX; \
    	BSWAPQ	AX; \
    	MOVQ	AX, (index*8)(BP)
    
    // Wt = SIGMA1(Wt-2) + Wt-7 + SIGMA0(Wt-15) + Wt-16; for 16 <= t <= 79
    //   SIGMA0(x) = ROTR(1,x) XOR ROTR(8,x) XOR SHR(7,x)
    //   SIGMA1(x) = ROTR(19,x) XOR ROTR(61,x) XOR SHR(6,x)
    #define MSGSCHEDULE1(index) \
    	MOVQ	((index-2)*8)(BP), AX; \
    	MOVQ	AX, CX; \
    	RORQ	$19, AX; \
    	MOVQ	CX, DX; \
    	RORQ	$61, CX; \
    	SHRQ	$6, DX; \
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 27K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go

    		{name: "ROTR", argLength: 2, reg: gp21, asm: "ROTR"},                      // arg0 right rotate by (arg1 mod 32) bits
    		{name: "ROTRV", argLength: 2, reg: gp21, asm: "ROTRV"},                    // arg0 right rotate by (arg1 mod 64) bits
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:04:19 UTC 2023
    - 25.2K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/LOONG64.rules

    (RotateLeft16 <t> x (MOVVconst [c])) => (Or16 (Lsh16x64 <t> x (MOVVconst [c&15])) (Rsh16Ux64 <t> x (MOVVconst [-c&15])))
    (RotateLeft32 x y) => (ROTR  x (NEGV <y.Type> y))
    (RotateLeft64 x y) => (ROTRV x (NEGV <y.Type> y))
    
    // unary ops
    (Neg(64|32|16|8) ...) => (NEGV ...)
    (Neg(32|64)F ...) => (NEG(F|D) ...)
    
    (Com(64|32|16|8) x) => (NOR (MOVVconst [0]) x)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 31.8K bytes
    - Viewed (0)
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