VPMULL	V1.D1, V2.H4, V3.Q1                              // ERROR "invalid arrangement"
	VPMULL	V1.H4, V2.H4, V3.Q1                              // ERROR "operand mismatch"
	VPMULL	V1.D2, V2.D2, V3.Q1                              // ERROR "operand mismatch"
	VPMULL	V1.B16, V2.B16, V3.H8                            // ERROR "operand mismatch"
	VPMULL2	V1.D2, V2.H4, V3.Q1                              // ERROR "invalid arrangement"

                .filter(q -> StringUtil.isNotBlank(q) && q.length() <= maxQueryLength)
                .forEach(oq -> split(oq, " ")
                        .get(s -> s.filter(StringUtil::isNotBlank).reduce((q1, q2) -> escape(q1, "(", ")") + OR + escape(q2, "(", ")")))
                        .ifPresent(q -> {
                            appendQuery(queryBuf, q);
                        })));

   * provided.
   */
  static final class Cell {
    volatile long p0, p1, p2, p3, p4, p5, p6;
    volatile long value;
    volatile long q0, q1, q2, q3, q4, q5, q6;

    Cell(long x) {
      value = x;
    }

    final boolean cas(long cmp, long val) {
      return UNSAFE.compareAndSwapLong(this, VALUE_OFFSET, cmp, val);
    }

			wantOk:       true,
		},
		{
			name:         "one-q1",
			m:            metaCacheEntries{inputSerialized[0], inputSerialized[4], inputSerialized[4], inputSerialized[4]},
			r:            metadataResolutionParams{dirQuorum: 1, objQuorum: 1, strict: false},
			wantSelected: &inputSerialized[0],
			wantOk:       true,
		},
		{
			name:         "one-q1-strict",

		case "D2":
			if isIndex {
				return errors.New("invalid register extension")
			}
			a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_2D & 15) << 5)
		case "Q1":
			if isIndex {
				return errors.New("invalid register extension")
			}
			a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_1Q & 15) << 5)
		case "B":
			if !isIndex {
				return nil
			}

	VMOVI $146, V22.B16                                         // 56e6044f
	VORR V25.B16, V22.B16, V15.B16                              // cf1eb94e
	VPMULL V2.D1, V1.D1, V3.Q1                                  // 23e0e20e
	VPMULL2 V2.D2, V1.D2, V4.Q1                                 // 24e0e24e
	VPMULL V2.B8, V1.B8, V3.H8                                  // 23e0220e
	VPMULL2 V2.B16, V1.B16, V4.H8                               // 24e0224e