Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 4 of 4 for H8 (0.03 sec)

  2. github.com/golang/go

    src/cmd/asm/internal/asm/testdata/arm64error.s 

    	VFMLA	V1.B16, V12.B16, V3.B16                          // ERROR "invalid arrangement"
	VFMLA	V1.H4, V12.H4, V3.H4                             // ERROR "invalid arrangement"
	VFMLA	V1.H8, V12.H8, V3.H8                             // ERROR "invalid arrangement"
	VFMLA	V1.H4, V12.H4, V3.H4                             // ERROR "invalid arrangement"
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Mar 26 10:48:50 UTC 2025
    - 37.9K bytes
    - Viewed (0)
  3. github.com/golang/go

    src/cmd/asm/internal/asm/testdata/arm64enc.s 

    	UCVTFD R20, F11                            // 8b02639e
	VADD V16, V19, V14                                          // 6e86f05e
	VADD V5.H8, V18.H8, V9.H8                                   // 4986654e
	VADDP V7.H8, V25.H8, V17.H8                                 // 31bf674e
	VADDV V3.H8, V0                                             // 60b8714e
	AESD V22.B16, V19.B16                                       // d35a284e
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Mon Jul 24 01:11:41 UTC 2023
    - 43.9K bytes
    - Viewed (0)
  4. github.com/golang/go

    src/cmd/asm/internal/arch/arm64.go 

    		case "H4":
			if isIndex {
				return errors.New("invalid register extension")
			}
			a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_4H & 15) << 5)
		case "H8":
			if isIndex {
				return errors.New("invalid register extension")
			}
			a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8H & 15) << 5)
		case "S2":
			if isIndex {
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Fri Feb 14 15:13:11 UTC 2025
    - 10.3K bytes
    - Viewed (0)
  5. github.com/golang/go

    src/cmd/asm/internal/asm/testdata/loong64enc1.s 

    	VMOVQ		V2.H[2], V8.H8  // 48c8f772
	VMOVQ		V3.W[1], V7.W4  // 67e4f772
	VMOVQ		V4.V[0], V6.V2  // 86f0f772

	// Load data from memory and broadcast to each element of a vector register: VMOVQ    offset(Rj), <Vd>.<T>
	VMOVQ		(R4), V0.B16	// 80008030
	VMOVQ		1(R4), V0.B16	// 80048030
	VMOVQ		-3(R4), V0.B16	// 80f4bf30
	VMOVQ		(R4), V1.H8	// 81004030
	VMOVQ		2(R4), V1.H8	// 81044030
	VMOVQ		-6(R4), V1.H8	// 81f45f30
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Thu Sep 04 19:24:25 UTC 2025
    - 35.5K bytes
    - Viewed (0)
Back to top