return true
	case DIVD, DIVDCC, DIVDU, DIVDUCC, DIVDE, DIVDECC, DIVDEU, DIVDEUCC, DIVDO, DIVDOCC, DIVDUO, DIVDUOCC:
		return true
	case MODUD, MODSD, MODUW, MODSW:
		return true
	case FADD, FADDS, FSUB, FSUBS, FMUL, FMULS, FDIV, FDIVS, FMADD, FMADDS, FMSUB, FMSUBS, FNMADD, FNMADDS, FNMSUB, FNMSUBS, FMULSCC:
		return true
	case FADDCC, FADDSCC, FSUBCC, FMULCC, FDIVCC, FDIVSCC:
		return true

		}

	case FST, FSTP, FISTTP, FIST, FISTP, FBSTP:
		if len(args) == 1 {
			args = append(args, "st0")
		}

	case FLD, FXCH, FCOM, FCOMP, FIADD, FIMUL, FICOM, FICOMP, FISUBR, FIDIV, FUCOM, FUCOMP, FILD, FBLD, FADD, FMUL, FSUB, FSUBR, FISUB, FDIV, FDIVR, FIDIVR:
		if len(args) == 1 {
			args = []string{"st0", args[0]}
		}

	case MASKMOVDQU, MASKMOVQ, XLATB, OUTSB, OUTSW, OUTSD:
	FixSegment:

// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

// Lowering arithmetic
(Add(Ptr|64|32|16|8) ...) => (ADD ...)
(Add(64|32)F ...) => (FADD(D|S) ...)

(Sub(Ptr|64|32|16|8) ...) => (SUB ...)
(Sub(64|32)F ...) => (FSUB(D|S) ...)

(Mul64 ...) => (MUL  ...)
(Mul64uhilo ...) => (LoweredMuluhilo ...)
(Mul64uover ...) => (LoweredMuluover ...)

	WFSDB	V0, V0, V2
	WORD	$0xED509298	//sdb	%f5,.L55-.L38(%r9)
	BYTE	$0x00
	BYTE	$0x1B
	FMOVD	640(R9), F6
	FMOVD	632(R9), F4
	WFMSDB	V5, V6, V2, V6
	WFMSDB	V5, V4, V0, V4
	FMOVD	624(R9), F2
	FADD	F6, F4
	FMOVD	616(R9), F0
	FMOVD	608(R9), F6
	WFMADB	V4, V0, V2, V0
	FMOVD	600(R9), F3
	WFMDB	V4, V4, V2
	MOVH	R6,R6
	ADD	R6, R3
	WFMADB	V4, V3, V6, V3
	FMOVD	592(R9), F6
	WFMADB	V0, V2, V3, V0

	FMOVD	F0, 4096(R1)           // ed0010000167
	FMOVS	F13, 4095(R2)(R3)      // 70d32fff
	FMOVS	F13, 4096(R2)(R3)      // edd320000166

	FADDS	F0, F15                // b30a00f0
	FADD	F1, F14                // b31a00e1
	FSUBS	F2, F13                // b30b00d2
	FSUB	F3, F12                // b31b00c3
	FMULS	F4, F11                // b31700b4
	FMUL	F5, F10                // b31c00a5

	case FCCMP, FCCMPE:
		args[0], args[1] = args[1], args[0]
		fallthrough

	case FCMP, FCMPE:
		if _, ok := inst.Args[1].(Imm); ok {
			args[1] = "$(0.0)"
		}
		fallthrough

	case FADD, FSUB, FMUL, FNMUL, FDIV, FMAX, FMIN, FMAXNM, FMINNM, FCSEL, FMADD, FMSUB, FNMADD, FNMSUB:
		if strings.HasSuffix(op, "MADD") || strings.HasSuffix(op, "MSUB") {
			args[2], args[3] = args[3], args[2]
		}

	WFMADB	V4, V6, V16, V16
	SLD	$3, R0, R2
	FMOVD	104(R9), F5
	WORD	$0xED824004	//ldeb	%f8,4(%r2,%r4)
	BYTE	$0x00
	BYTE	$0x04
	LDEBR	F3, F3
	FMOVD	96(R9), F6
	WFMADB	V4, V6, V5, V6
	FADD	F8, F3
	WFMADB	V7, V6, V16, V6
	FMUL	F7, F7
	FMOVD	88(R9), F5
	FMADD	F7, F1, F6
	WFMADB	V4, V5, V3, V16
	FMOVD	80(R9), F1
	WFSDB	V16, V3, V3
	MOVD	$·powtl<>+0(SB), R3
	WFMADB	V4, V6, V1, V6

	}
	return ""
}

func argBytes(inst *Inst, arg Arg) int {
	if isMem(arg) {
		return inst.MemBytes
	}
	return regBytes(arg)
}

func isFloat(op Op) bool {
	switch op {
	case FADD, FCOM, FCOMP, FDIV, FDIVR, FIADD, FICOM, FICOMP, FIDIV, FIDIVR, FILD, FIMUL, FIST, FISTP, FISTTP, FISUB, FISUBR, FLD, FMUL, FST, FSTP, FSUB, FSUBR:
		return true
	}
	return false
}

func isFloatInt(op Op) bool {

		{name: "ADDCCconst", argLength: 1, reg: gp11cxer, asm: "ADDCCC", aux: "Int64", typ: "(Int,Flags)"}, // arg0 + auxInt sets CC, clobbers XER
		{name: "FADD", argLength: 2, reg: fp21, asm: "FADD", commutative: true},                            // arg0+arg1
		{name: "FADDS", argLength: 2, reg: fp21, asm: "FADDS", commutative: true},                          // arg0+arg1