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Results 1 - 4 of 4 for AMUL (0.03 sec)
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src/cmd/internal/obj/riscv/cpu.go
AADDIW ASLLIW ASRLIW ASRAIW AADDW ASLLW ASRLW ASUBW ASRAW // 5.3: Load and Store Instructions (RV64I) ALD ASD // 7.1: Multiplication Operations AMUL AMULH AMULHU AMULHSU AMULW ADIV ADIVU AREM AREMU ADIVW ADIVUW AREMW AREMUW // 8.2: Load-Reserved/Store-Conditional Instructions ALRD ASCD ALRW
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.1K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/inst.go
return &inst{0x33, 0x7, 0x0, 160, 0x5} case AMIN: return &inst{0x33, 0x4, 0x0, 160, 0x5} case AMINU: return &inst{0x33, 0x5, 0x0, 160, 0x5} case AMRET: return &inst{0x73, 0x0, 0x2, 770, 0x18} case AMUL: return &inst{0x33, 0x0, 0x0, 32, 0x1} case AMULH: return &inst{0x33, 0x1, 0x0, 32, 0x1} case AMULHSU: return &inst{0x33, 0x2, 0x0, 32, 0x1} case AMULHU: return &inst{0x33, 0x3, 0x0, 32, 0x1}
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.9K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/a.out.go
AMOVHU AMOVK AMOVKW AMOVN AMOVNW AMOVP AMOVPD AMOVPQ AMOVPS AMOVPSW AMOVPW AMOVW AMOVWU AMOVZ AMOVZW AMRS AMSR AMSUB AMSUBW AMUL AMULW AMVN AMVNW ANEG ANEGS ANEGSW ANEGW ANGC ANGCS ANGCSW ANGCW ANOOP AORN AORNW AORR AORRW APRFM APRFUM ARBIT ARBITW
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 18 17:56:30 UTC 2023 - 18.1K bytes - Viewed (0) -
src/cmd/internal/obj/mips/obj0.go
case AMOVF, AMOVW, AMOVWL, AMOVWR: sz = 4 ld = 1 case AMOVD, AMOVV, AMOVVL, AMOVVR: sz = 8 ld = 1 case ADIV, ADIVU, AMUL, AMULU, AREM, AREMU, ADIVV, ADIVVU, AMULV, AMULVU, AREMV, AREMVU: s.set.cc = E_HILO fallthrough case AADD, AADDU, AADDV,
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 19:28:53 UTC 2023 - 30.6K bytes - Viewed (0)