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src/cmd/asm/internal/asm/testdata/riscv64validation.s
VMSLTVI $17, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" VMSLTVI $-16, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" VMSLTUVI $17, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]" VMSLTUVI $-16, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]" VMSGEVI $17, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]"
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed May 21 14:19:19 UTC 2025 - 31.6K bytes - Viewed (0) -
src/config/eclipse/formatter/java.xml
<setting id="org.eclipse.jdt.core.formatter.insert_space_after_comma_in_method_invocation_arguments" value="insert"/> <setting id="org.eclipse.jdt.core.formatter.alignment_for_arguments_in_method_invocation" value="16"/> <setting id="org.eclipse.jdt.core.formatter.alignment_for_throws_clause_in_constructor_declaration" value="16"/>
Registered: Fri Sep 19 09:08:11 UTC 2025 - Last Modified: Mon Mar 23 21:27:06 UTC 2015 - 30.5K bytes - Viewed (0) -
src/config/eclipse/formatter/javascript.xml
<setting id="org.eclipse.wst.jsdt.core.formatter.alignment_for_parameters_in_constructor_declaration" value="16"/> <setting id="org.eclipse.wst.jsdt.core.formatter.alignment_for_throws_clause_in_constructor_declaration" value="16"/> <setting id="org.eclipse.wst.jsdt.core.formatter.insert_space_before_opening_brace_in_type_declaration" value="insert"/>
Registered: Fri Sep 19 09:08:11 UTC 2025 - Last Modified: Mon Mar 23 21:27:06 UTC 2015 - 29.2K bytes - Viewed (0) -
src/cmd/asm/internal/asm/operand_test.go
{"$1", "$1"}, {"$-1", "$-1"}, {"$1000", "$1000"}, {"$1000000000", "$1000000000"}, {"$0x7fff3c000", "$34358935552"}, {"$1234", "$1234"}, {"$~15", "$-16"}, {"$16", "$16"}, {"-16(RSP)", "-16(RSP)"}, {"16(RSP)", "16(RSP)"}, {"1(R1)", "1(R1)"}, {"-1(R4)", "-1(R4)"}, {"18740(R5)", "18740(R5)"}, {"$2", "$2"}, {"$-24(R4)", "$-24(R4)"}, {"-24(RSP)", "-24(RSP)"}, {"$24(RSP)", "$24(RSP)"},Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Tue Aug 29 18:31:05 UTC 2023 - 23.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
ABSF F4, F5 // 85041401 MOVVF F4, F5 // 85181d01 MOVF F4, F5 // 85941401 MOVD F4, F5 // 85981401 MOVW R4, result+16(FP) // 64608029 MOVWU R4, result+16(FP) // 64608029 MOVV R4, result+16(FP) // 6460c029 MOVB R4, result+16(FP) // 64600029 MOVBU R4, result+16(FP) // 64600029 MOVW R4, 1(R5) // a4048029 MOVWU R4, 1(R5) // a4048029 MOVV R4, 1(R5) // a404c029 MOVB R4, 1(R5) // a4040029
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Thu Sep 04 19:24:25 UTC 2025 - 35.5K bytes - Viewed (0) -
lib/wasm/wasm_exec.js
sp >>>= 0; const result = Reflect.get(loadValue(sp + 8), loadString(sp + 16)); sp = this._inst.exports.getsp() >>> 0; // see comment above storeValue(sp + 32, result); }, // func valueSet(v ref, p string, x ref) "syscall/js.valueSet": (sp) => { sp >>>= 0; Reflect.set(loadValue(sp + 8), loadString(sp + 16), loadValue(sp + 32)); }, // func valueDelete(v ref, p string)
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Sun Dec 08 15:34:47 UTC 2024 - 16.6K bytes - Viewed (0) -
doc/asm.html
The order of the code modifiers is irrelevant. </p> <p> Addressing modes: </p> <ul> <li> <code>R0->16</code> <br> <code>R0>>16</code> <br> <code>R0<<16</code> <br> <code>R0@>16</code>: For <code><<</code>, left shift <code>R0</code> by 16 bits. The other codes are <code>-></code> (arithmetic right shift), <code>>></code> (logical right shift), and
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Tue Nov 28 19:15:27 UTC 2023 - 36.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
MOVBU 9(R19), R18 // 92720009 MOVBU -10(R19), R18 // 9272fff6 // // load floats // // LFMOV addr ',' freg // { // outcode(int($1), &$2, 0, &$4); // } MOVD foo<>+3(SB), F2 MOVD 16(R1), F2 MOVD (R1), F2 // LFMOV fimm ',' freg // { // outcode(int($1), &$2, 0, &$4); // } MOVD $0.1, F2 // MOVD $(0.10000000000000001), F2 // LFMOV freg ',' freg // {
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64error.s
VNCLIPUWX X10, V2, V4, V3 // ERROR "invalid vector mask register" VNCLIPUWI $16, V2, V4, V3 // ERROR "invalid vector mask register" VNCLIPWV V1, V2, V4, V3 // ERROR "invalid vector mask register" VNCLIPWX X10, V2, V4, V3 // ERROR "invalid vector mask register" VNCLIPWI $16, V2, V4, V3 // ERROR "invalid vector mask register" VFADDVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Thu May 08 08:53:43 UTC 2025 - 24.8K bytes - Viewed (0) -
src/archive/tar/strconv_test.go
{"1 k=1\n", "1 k=1\n", "", "", false}, {"6 k~1\n", "6 k~1\n", "", "", false}, {"6_k=1\n", "6_k=1\n", "", "", false}, {"6 k=1 ", "6 k=1 ", "", "", false}, {"632 k=1\n", "632 k=1\n", "", "", false}, {"16 longkeyname=hahaha\n", "16 longkeyname=hahaha\n", "", "", false}, {"3 somelongkey=\n", "3 somelongkey=\n", "", "", false}, {"50 tooshort=\n", "50 tooshort=\n", "", "", false},Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Mon Sep 08 17:08:20 UTC 2025 - 15K bytes - Viewed (0)