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Results 1 - 3 of 3 for SEQZ (0.14 sec)

  1. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (BGE cond (MOVDconst [0]) yes no) => (BGEZ cond yes no)
    
    // Remove redundant NEG from SEQZ/SNEZ.
    (SEQZ (NEG x)) => (SEQZ x)
    (SNEZ (NEG x)) => (SNEZ x)
    
    // Remove redundant SEQZ/SNEZ.
    (SEQZ (SEQZ x)) => (SNEZ x)
    (SEQZ (SNEZ x)) => (SEQZ x)
    (SNEZ (SEQZ x)) => (SEQZ x)
    (SNEZ (SNEZ x)) => (SNEZ x)
    
    // Store zero.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

    		{name: "XORI", argLength: 1, reg: gp11, asm: "XORI", aux: "Int64"},    // arg0 ^ auxint
    
    		// Generate boolean values
    		{name: "SEQZ", argLength: 1, reg: gp11, asm: "SEQZ"},                 // arg0 == 0, result is 0 or 1
    		{name: "SNEZ", argLength: 1, reg: gp11, asm: "SNEZ"},                 // arg0 != 0, result is 0 or 1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 30.7K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/riscv64.s

    	BLE	X5, X6, 2(PC)				// 63545300
    	BLEU	X5, X6, 2(PC)				// 63745300
    	BLEZ	X5, 2(PC)				// 63545000
    	BLTZ	X5, 2(PC)				// 63c40200
    	BNEZ	X5, 2(PC)				// 63940200
    
    	// Set pseudo-instructions
    	SEQZ	X15, X15				// 93b71700
    	SNEZ	X15, X15				// b337f000
    
    	// F extension
    	FABSS	F0, F1					// d3200020
    	FNEGS	F0, F1					// d3100020
    	FNES	F0, F1, X7				// d3a300a093c31300
    
    	// D extension
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 22 04:42:21 UTC 2024
    - 16.7K bytes
    - Viewed (0)
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