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Results 1 - 5 of 5 for fpscrx (0.11 sec)
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src/runtime/mkpreempt.go
for i := 0; i <= 31; i++ { reg := fmt.Sprintf("F%d", i) l.add("FMOVD", reg, 8) } // Add floating point control/status register FPSCR. l.addSpecial( "MOVFL FPSCR, F0\nFMOVD F0, %d(R1)", "FMOVD %d(R1), F0\nMOVFL F0, FPSCR", 8) p("MOVD R31, -%d(R1)", l.stack-32) // save R31 first, we'll use R31 for saving LR p("MOVD LR, R31")
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 15.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
// outcode(int($1), &$2, 0, &$4); // } MOVD F1, foo<>+3(SB) MOVD F1, 16(R2) MOVD F1, (R2) // // floating point status // // LMOVW fpscr ',' freg // { // outcode(int($1), &$2, 0, &$4); // } MOVW FCR31, R1 // 4441f800 // LMOVW freg ',' fpscr // { // outcode(int($1), &$2, 0, &$4); // } MOVW R1, FCR31 // 44c1f800 // LMOVW rreg ',' mreg // { // outcode(int($1), &$2, 0, &$4);
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/a.out.go
C_SOREG /* An $n+reg memory arg where n is a 16 bit signed offset */ C_LOREG /* An $n+reg memory arg where n is a 32 bit signed offset */ C_XOREG /* An reg+reg memory arg */ C_FPSCR /* The fpscr register */ C_LR /* The link register */ C_CTR /* The count register */ C_ANY /* Any argument */ C_GOK /* A non-matched argument */ C_ADDR /* A symbolic memory location */
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 16K bytes - Viewed (0) -
src/runtime/asm_arm.s
// disable runfast (flush-to-zero) mode of vfp if runtime.goarmsoftfp == 0 MOVB runtime·goarmsoftfp(SB), R11 CMP $0, R11 BNE 4(PC) WORD $0xeef1ba10 // vmrs r11, fpscr BIC $(1<<24), R11 WORD $0xeee1ba10 // vmsr fpscr, r11 RET TEXT runtime·mstart(SB),NOSPLIT|TOPFRAME,$0 BL runtime·mstart0(SB) RET // not reached /* * go-routine */ // void gogo(Gobuf*)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 23 21:00:52 UTC 2024 - 32.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
gpfp = regInfo{inputs: []regMask{gp}, outputs: []regMask{fp}} fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}} fp31 = regInfo{inputs: []regMask{fp, fp, fp}, outputs: []regMask{fp}} fp2cr = regInfo{inputs: []regMask{fp, fp}} fpload = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{fp}} fploadidx = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{fp}}
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0)