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src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 30.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
FNEGS F0, F1 // d3100020 FNES F0, F1, X7 // d3a300a093c31300 // D extension FABSD F0, F1 // d3200022 FNEGD F0, F1 // d3100022 FNED F0, F1, X5 // d3a200a293c21200 FLTD F0, F1, X5 // d39200a2 FLED F0, F1, X5 // d38200a2 FEQD F0, F1, X5 // d3a200a2
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 22 04:42:21 UTC 2024 - 16.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64.rules
(MOVDstore [off] {sym} ptr (MOVDconst [0]) mem) => (MOVDstorezero [off] {sym} ptr mem) // Boolean ops are already extended. (MOVBUreg x:((FLES|FLTS|FEQS|FNES) _ _)) => x (MOVBUreg x:((FLED|FLTD|FEQD|FNED) _ _)) => x (MOVBUreg x:((SEQZ|SNEZ) _)) => x (MOVBUreg x:((SLT|SLTU) _ _)) => x // Avoid extending when already sufficiently masked. (MOVBreg x:(ANDI [c] y)) && c >= 0 && int64(int8(c)) == c => x
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 40.3K bytes - Viewed (0)