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Results 1 - 10 of 129 for z0 (0.02 sec)

  1. pkg/apis/resource/validation/validation_resourceslice_test.go

    			slice:        testResourceSlice(badName, goodName, driverName),
    		},
    		"generate-name": {
    			slice: func() *resource.ResourceSlice {
    Registered: Sat Jun 15 01:39:40 UTC 2024
    - Last Modified: Thu Mar 14 17:07:36 UTC 2024
    - 8.9K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/tensorflow/tests/tpu_update_embedding_enqueue_op_inputs.mlir

    // CHECK-SAME: %[[ARG_0:[a-z0-9]*]]: tensor<?x2xi32>
    // CHECK-SAME: %[[ARG_1:[a-z0-9]*]]: tensor<?x2xi32>
    // CHECK-SAME: %[[ARG_2:[a-z0-9]*]]: tensor<?x2xi32>
    // CHECK-SAME: %[[ARG_3:[a-z0-9]*]]: tensor<?xi32>
    // CHECK-SAME: %[[ARG_4:[a-z0-9]*]]: tensor<?xi32>
    // CHECK-SAME: %[[ARG_5:[a-z0-9]*]]: tensor<?xi32>
    // CHECK-SAME: %[[ARG_6:[a-z0-9]*]]: tensor<!tf_type.string>
    // CHECK-SAME: %[[ARG_7:[a-z0-9]*]]: tensor<!tf_type.string>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 5.3K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/tensorflow/tests/remove_unused_while_results.mlir

    // CHECK:       tf.WhileRegion
    // CHECK-SAME:    (%[[ARG0:[a-zA-Z0-9_]+]], %[[ARG1:[a-zA-Z0-9_]+]])
    // CHECK:       ^bb0
    // CHECK:         (%[[CARG0:[a-zA-Z0-9_]+]]: tensor<*xf32>, %[[CARG1:[a-zA-Z0-9_]+]]: tensor<*xf32>)
    // CHECK:       tf.OpA
    // CHECK:       ^bb0
    // CHECK:         (%[[BARG0:[a-zA-Z0-9_]+]]: tensor<*xf32>, %[[BARG1:[a-zA-Z0-9_]+]]: tensor<*xf32>)
    // CHECK:       tf.OpB
    // CHECK:       tf.OpC
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Sep 21 20:25:31 UTC 2022
    - 8.5K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/tensorflow/tests/tf_device_ops.mlir

      }
      func.return
    
    // CHECK:      %[[OP_A:[a-z0-9]*]] = "tf.opA"
    // CHECK:      %[[OP_B:[a-z0-9]*]] = "tf.opB"
    // CHECK:      %[[OP_C:[a-z0-9]*]] = "tf.opC"
    // CHECK:      %[[OP_D:[a-z0-9]*]] = "tf.opD"
    // CHECK:      %[[OP_E:[a-z0-9]*]] = "tf.opE"
    // CHECK:      %[[OP_F:[a-z0-9]*]] = "tf.opF"
    // CHECK:      %[[OP_G:[a-z0-9]*]] = "tf.opG"
    // CHECK:      %[[OP_H:[a-z0-9]*]] = "tf.opH"
    // CHECK:      %[[OP_I:[a-z0-9]*]] = "tf.opI"
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Jan 23 23:53:20 UTC 2024
    - 7.7K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/fuse_test.go

    		}
    	}
    
    	// Case2, z0 contains a value that has side effect, z0 shouldn't be eliminated.
    	//     entry
    	//      | \
    	//      |  z0
    	//      | /
    	//     exit
    	fun = c.Fun("entry",
    		Bloc("entry",
    			Valu("mem", OpInitMem, types.TypeMem, 0, nil),
    			Valu("c1", OpArg, c.config.Types.Bool, 0, nil),
    			Valu("p", OpArg, c.config.Types.IntPtr, 0, nil),
    			If("c1", "z0", "exit")),
    		Bloc("z0",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Oct 31 20:45:54 UTC 2023
    - 7.4K bytes
    - Viewed (0)
  6. staging/src/k8s.io/apiserver/pkg/cel/library/format_test.go

    		},
    		{
    			name:        "dns1035Label",
    			expr:        `format.dns1035Label().validate("contains a space")`,
    Registered: Sat Jun 15 01:39:40 UTC 2024
    - Last Modified: Tue Apr 23 17:22:44 UTC 2024
    - 9.2K bytes
    - Viewed (0)
  7. tensorflow/compiler/mlir/tensorflow/tests/graphdef2mlir/add.pbtxt

    # NONE-SAME:  (%[[ARG_0:[a-z0-9]+]]: tensor<10xi32>, %[[ARG_1:[a-z0-9]+]]: tensor<10xi32>) -> tensor<*xi32>
    # NONE-SAME:  control_outputs = ""
    # NONE-SAME:  inputs = "input0,input1"
    # NONE-SAME:  outputs = "Add"
    # NONE:           %[[add:.*]], %[[add_control:.*]] = tf_executor.island wraps "tf.Add"(%[[ARG_0]], %[[ARG_1]])
    # NONE:           fetch %[[add]]
    
    # UNKNOWN-LABEL: func @main
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Nov 17 08:38:39 UTC 2020
    - 3.4K bytes
    - Viewed (0)
  8. src/cmd/asm/internal/asm/testdata/avx512enc/avx512_4vnniw.s

    	VP4DPWSSDS -7(DI)(R8*1), [Z4-Z7], K1, Z0           // 62b25f49538407f9ffffff
    	VP4DPWSSDS (SP), [Z4-Z7], K1, Z0                   // 62f25f49530424
    	VP4DPWSSDS -7(DI)(R8*1), [Z14-Z17], K1, Z0         // 62b20f49538407f9ffffff
    	VP4DPWSSDS (SP), [Z14-Z17], K1, Z0                 // 62f20f49530424
    	VP4DPWSSDS -7(DI)(R8*1), [Z24-Z27], K1, Z0         // 62b23f41538407f9ffffff
    	VP4DPWSSDS (SP), [Z24-Z27], K1, Z0                 // 62f23f41530424
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 22 14:57:15 UTC 2018
    - 1.9K bytes
    - Viewed (0)
  9. src/cmd/asm/internal/asm/testdata/avx512enc/avx512_4fmaps.s

    TEXT asmtest_avx512_4fmaps(SB), NOSPLIT, $0
    	V4FMADDPS 17(SP), [Z0-Z3], K2, Z0                  // 62f27f4a9a842411000000
    	V4FMADDPS -17(BP)(SI*4), [Z0-Z3], K2, Z0           // 62f27f4a9a84b5efffffff
    	V4FMADDPS 17(SP), [Z10-Z13], K2, Z0                // 62f22f4a9a842411000000
    	V4FMADDPS -17(BP)(SI*4), [Z10-Z13], K2, Z0         // 62f22f4a9a84b5efffffff
    	V4FMADDPS 17(SP), [Z20-Z23], K2, Z0                // 62f25f429a842411000000
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 22 14:57:15 UTC 2018
    - 5.9K bytes
    - Viewed (0)
  10. src/crypto/internal/bigmod/_asm/nat_amd64_asm.go

    	z = Mem{Base: Load(Param("z"), GP64())}
    	x = Mem{Base: Load(Param("x"), GP64())}
    	Load(Param("y"), RDX) // implicit source of MULXQ
    
    	carry = GP64()
    	XORQ(carry, carry) // zero out carry
    	z0 := GP64()
    	XORQ(z0, z0) // unset flags and zero out z0
    
    	for i := 0; i < bits/64; i++ {
    		hi, lo := GP64(), GP64()
    
    		Comment("Iteration " + strconv.Itoa(i))
    		MULXQ(x.Offset(i*8), lo, hi)
    		ADCXQ(carry, lo)
    		ADOXQ(z.Offset(i*8), lo)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 22:37:58 UTC 2023
    - 2.5K bytes
    - Viewed (0)
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