//	}
	SLL	R1, R2

	//	LSHW imm ',' sreg ',' rreg
	//	{
	//		outcode(int($1), &$2, int($4), &$6);
	//	}
	SLL	$4, R1, R2

	//	LSHW imm ',' rreg
	//	{
	//		outcode(int($1), &$2, 0, &$4);
	//	}
	SLL	$4, R1

	//
	// move immediate: macro for lui+or, addi, addis, and other combinations
	//
	//	LMOVW imm ',' rreg
	//	{
	//		outcode(int($1), &$2, 0, &$4);
	//	}

// CSR symbolic names and whether that instruction expects a register
// or an immediate source operand.
func IsRISCV64CSRO(op obj.As) (imm bool, ok bool) {
	switch op {
	case riscv.ACSRRCI, riscv.ACSRRSI, riscv.ACSRRWI:
		imm = true
		fallthrough
	case riscv.ACSRRC, riscv.ACSRRS, riscv.ACSRRW:
		ok = true
	}
	return
}

var riscv64SpecialOperand map[string]riscv.SpecialOperand