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Results 1 - 10 of 11 for fusedBatchNormV3 (0.42 sec)

  1. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_to_nhwc.mlir

      // CHECK-SAME: %[[PAD]]
      // CHECK-SAME: data_format = "NHWC"
      // CHECK-SAME: strides = [1, 2, 2, 1]
    
      %6, %batch_mean, %batch_variance, %reserved_1, %reserved_2, %reserved_3 =
           "tf.FusedBatchNormV3"(%5, %arg1, %arg1, %arg1, %arg1)
           {
             data_format = "NCHW",
             epsilon = 1.001000e-05 : f32,
             is_training = false
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 7.3K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_gpu_cc_60.mlir

      %arg0: tensor<1x28x28x64xf32>,
      %arg1: tensor<64xf32>
    ) -> tensor<1x28x28x64xf32> {
    
      // CHECK: "tf.FusedBatchNormV3"
      // CHECK-SAME: (%[[X_TRANSPOSE:[0-9]*]], %arg1, %arg1, %arg1, %arg1)
      // CHECK-SAME: data_format = "NCHW"
      %y, %batch_mean, %batch_var, %reserve_1, %reserve_2, %reserve_3
        = "tf.FusedBatchNormV3"(%arg0, %arg1, %arg1, %arg1, %arg1)
           {
             data_format = "NHWC",
             epsilon = 1.001 : f32,
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Jun 21 08:41:18 UTC 2022
    - 5.8K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/tensorflow/tests/gpu_fusion.mlir

    // CHECK-NEXT: %[[Y:[a-z0-9]*]], {{.*}}_FusedBatchNormEx
    // CHECK-NEXT: return %[[Y]]
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Mar 24 05:47:26 UTC 2022
    - 3.6K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/tensorflow/transforms/gpu_fusion.cc

     public:
      void runOnOperation() final;
    };
    
    //   %y:6 = "tf.FusedBatchNormV3"(%x, %scale, %offset, %mean, %variance)
    //   %0 = "tf.Relu"(%y#0)
    // ->
    //   %y:6 = "tf._FusedBatchNormEx"(%x, %scale, %offset, %mean, %variance)
    //
    // Or:
    //   %y:6 = "tf.FusedBatchNormV3"(%x, %scale, %offset, %mean, %variance)
    //   %0 = "tf.AddV2"(%y#0, %side_input)
    //   %1 = "tf.Relu"(%0)
    // ->
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Nov 03 12:35:38 UTC 2022
    - 5.2K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/lite/tests/prepare-tf-with-allowing-bf16-and-f16-type-legalization.mlir

    func.func @fused_batch_norm_v3_bf16(%arg0: tensor<8x8x8x8xbf16>, %arg1: tensor<8xf32>, %arg2: tensor<8xf32>, %arg3: tensor<8xf32>, %arg4: tensor<8xf32>) -> tensor<8x8x8x8xbf16> {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 26 23:53:32 UTC 2022
    - 2.2K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_gpu_cc_70.mlir

      %arg0: tensor<1x28x28x64xf32>,
      %arg1: tensor<64xf32>
    ) -> tensor<1x28x28x64xf32> {
    
      // CHECK: "tf.FusedBatchNormV3"
      // CHECK-SAME: (%[[X_TRANSPOSE:[0-9]*]], %arg1, %arg1, %arg1, %arg1)
      // CHECK-SAME: data_format = "NCHW"
      %y, %batch_mean, %batch_var, %reserve_1, %reserve_2, %reserve_3
        = "tf.FusedBatchNormV3"(%arg0, %arg1, %arg1, %arg1, %arg1)
           {
             data_format = "NHWC",
             epsilon = 1.001 : f32,
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Jun 21 08:41:18 UTC 2022
    - 8.5K bytes
    - Viewed (0)
  7. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_to_nhwc.mlir

      // CHECK: %[[ARG_PERM:.*]] = "tf.Const"()
      // CHECK-SAME: <{value = dense<[0, 2, 3, 1]> : tensor<4xi64>}>
      // CHECK: %[[ARG_TRANSPOSE:[0-9]*]] = "tf.Transpose"(%arg0, %[[ARG_PERM]])
    
      // CHECK: "tf.FusedBatchNormV3"
      // CHECK-SAME: (%[[ARG_TRANSPOSE]], %arg1, %arg1, %arg1, %arg1)
      // CHECK-SAME: data_format = "NHWC"
      // CHECK-SAME: (tensor<1x28x28x64xf32>, tensor<64xf32>,
      // CHECK-SAME: -> (tensor<1x28x28x64xf32>, tensor<64xf32>,
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 4.5K bytes
    - Viewed (0)
  8. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_move_transposes_end.mlir

      %1 = "tf.Transpose"(%arg0, %0) : (tensor<1x64x112x112xf32>, tensor<4xi32>) -> tensor<1x112x112x64xf32>
    
      // Compute FusedBatchNormV3 in NHWC format
      %2, %batch_mean, %batch_var, %reserve_1, %reserve_2, %reserve_3
        = "tf.FusedBatchNormV3"(%1, %arg1, %arg1, %arg1, %arg1)
           {
             data_format = "NHWC",
             epsilon = 1.001 : f32,
             exponential_avg_factor = 1.0 : f32,
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 9.5K bytes
    - Viewed (0)
  9. tensorflow/compiler/mlir/tensorflow/tests/compile_mlir_util/shape-inference-after-legalization.mlir

      func.func @main(%arg0: tensor<8x16x16x64xbf16>, %arg1: tensor<64xf32>) -> (tensor<8x16x16x64xbf16>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<*xf32>) {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Mar 23 18:56:13 UTC 2022
    - 1.2K bytes
    - Viewed (0)
  10. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_to_nchw.mlir

      // CHECK: %[[ARG_PERM:.*]] = "tf.Const"()
      // CHECK-SAME: <{value = dense<[0, 3, 1, 2]> : tensor<4xi64>}>
      // CHECK: %[[ARG_TRANSPOSE:[0-9]*]] = "tf.Transpose"(%arg0, %[[ARG_PERM]])
    
      // CHECK: "tf.FusedBatchNormV3"
      // CHECK-SAME: (%[[ARG_TRANSPOSE]], %arg1, %arg1, %arg1, %arg1)
      // CHECK-SAME: data_format = "NCHW"
      // CHECK-SAME: (tensor<1x64x28x28xf32>, tensor<64xf32>,
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 9K bytes
    - Viewed (0)
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