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Results 1 - 3 of 3 for AESD (0.02 sec)
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src/crypto/aes/asm_arm64.s
VLD1.P 48(R10), [V13.B16, V14.B16, V15.B16] AESD V5.B16, V0.B16 AESIMC V0.B16, V0.B16 AESD V6.B16, V0.B16 AESIMC V0.B16, V0.B16 AESD V7.B16, V0.B16 AESIMC V0.B16, V0.B16 AESD V8.B16, V0.B16 AESIMC V0.B16, V0.B16 AESD V9.B16, V0.B16 AESIMC V0.B16, V0.B16 AESD V10.B16, V0.B16 AESIMC V0.B16, V0.B16 AESD V11.B16, V0.B16 AESIMC V0.B16, V0.B16 AESD V12.B16, V0.B16 AESIMC V0.B16, V0.B16
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 6.9K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/doc.go
VADD V5.H8, V18.H8, V9.H8 <=> add v9.8h, v18.8h, v5.8h VLD1.P (R6)(R11), [V31.D1] <=> ld1 {v31.1d}, [x6], x11 VFMLA V29.S2, V20.S2, V14.S2 <=> fmla v14.2s, v20.2s, v29.2s AESD V22.B16, V19.B16 <=> aesd v19.16b, v22.16b SCVTFWS R3, F16 <=> scvtf s17, w6 6. Align directive Go asm supports the PCALIGN directive, which indicates that the next instruction should be aligned
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Aug 07 00:21:42 UTC 2023 - 9.6K bytes - Viewed (0) -
src/internal/buildcfg/cfg.go
return } type Goarm64Features struct { Version string // Large Systems Extension LSE bool // ARM v8.0 Cryptographic Extension. It includes the following features: // * FEAT_AES, which includes the AESD and AESE instructions. // * FEAT_PMULL, which includes the PMULL, PMULL2 instructions. // * FEAT_SHA1, which includes the SHA1* instructions. // * FEAT_SHA256, which includes the SHA256* instructions. Crypto bool }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 21 20:08:06 UTC 2024 - 9.5K bytes - Viewed (0)