- Sort Score
- Result 10 results
- Languages All
Results 31 - 40 of 70 for fdiv (0.03 sec)
-
src/cmd/asm/internal/arch/mips.go
return true } return false } // IsMIPSMUL reports whether the op (as defined by an mips.A* constant) is // one of the MUL/DIV/REM/MADD/MSUB instructions that require special handling. func IsMIPSMUL(op obj.As) bool { switch op { case mips.AMUL, mips.AMULU, mips.AMULV, mips.AMULVU, mips.ADIV, mips.ADIVU, mips.ADIVV, mips.ADIVVU, mips.AREM, mips.AREMU, mips.AREMV, mips.AREMVU, mips.AMADD, mips.AMSUB: return true }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 04 19:06:44 UTC 2020 - 1.7K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/experimental/tac/py_wrapper/BUILD
"@farmhash_archive//:__subpackages__", "@farmhash_gpu_archive//:__subpackages__", "@fft2d//:__subpackages__", "@flatbuffers//:__subpackages__", "@FP16//:__subpackages__", "@FXdiv//:__subpackages__", "@gemmlowp//:__subpackages__", "@gif//:__subpackages__", "@highwayhash//:__subpackages__", "@hwloc//:__subpackages__", "@icu//:__subpackages__",
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Mar 27 18:00:18 UTC 2024 - 4.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 30.7K bytes - Viewed (0) -
src/math/exp_arm64.s
FMOVD $P1, F12 // F12 = P1 FMADDD F7, F12, F13, F13 // P1+t*(P2+t*(P3+t*(P4+t*P5))) FMSUBD F7, F6, F13, F13 // F13 = c = r - t*(P1+t*(P2+t*(P3+t*(P4+t*P5)))) FMOVD $2.0, F14 FSUBD F13, F14 FMULD F6, F13, F15 FDIVD F14, F15 // F15 = (r*c)/(2-c) FSUBD F15, F5, F15 // lo-(r*c)/(2-c) FSUBD F4, F15, F15 // (lo-(r*c)/(2-c))-hi FSUBD F15, F1, F16 // F16 = y = 1-((lo-(r*c)/(2-c))-hi) // inline Ldexp(y, k), benefit:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Apr 15 15:48:19 UTC 2021 - 5.4K bytes - Viewed (0) -
src/math/hypot_386.s
FTST // compare F0 to 0 FSTSW AX ANDW $0x4000, AX JNE 10(PC) // jump if F0 = 0 FXCHD F0, F1 // F0=q (smaller), F1=p (larger) FDIVD F1, F0 // F0=q(=q/p), F1=p FMULD F0, F0 // F0=q*q, F1=p FLD1 // F0=1, F1=q*q, F2=p FADDDP F0, F1 // F0=1+q*q, F1=p FSQRT // F0=sqrt(1+q*q), F1=p
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Apr 15 15:48:19 UTC 2021 - 1.8K bytes - Viewed (0) -
src/cmd/asm/internal/arch/loong64.go
} return false } // IsLoong64MUL reports whether the op (as defined by an loong64.A* constant) is // one of the MUL/DIV/REM instructions that require special handling. func IsLoong64MUL(op obj.As) bool { switch op { case loong64.AMUL, loong64.AMULU, loong64.AMULV, loong64.AMULVU, loong64.ADIV, loong64.ADIVU, loong64.ADIVV, loong64.ADIVVU, loong64.AREM, loong64.AREMU, loong64.AREMV, loong64.AREMVU: return true }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 2.1K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/a.out.go
ACMPGTD // ACMPGTD -> fcmp.slt.d ACMPGTF // ACMPGTF -> fcmp.slt.s ALU12IW ALU32ID ALU52ID APCALAU12I APCADDU12I AJIRL ABGE ABLT ABLTU ABGEU ADIV ADIVD ADIVF ADIVU ADIVW ALL ALLV ALUI AMOVB AMOVBU AMOVD AMOVDF AMOVDW AMOVF AMOVFD AMOVFW AMOVH AMOVHU
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 5.7K bytes - Viewed (0) -
src/cmd/internal/obj/mips/a.out.go
ABGEZAL ABGTZ ABLEZ ABLTZ ABLTZAL ABNE ABREAK ACLO ACLZ ACMOVF ACMOVN ACMOVT ACMOVZ ACMPEQD ACMPEQF ACMPGED ACMPGEF ACMPGTD ACMPGTF ADIV ADIVD ADIVF ADIVU ADIVW AGOK ALL ALLV ALUI AMADD AMOVB AMOVBU AMOVD AMOVDF AMOVDW AMOVF AMOVFD AMOVFW AMOVH AMOVHU AMOVW
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 7.6K bytes - Viewed (0) -
src/cmd/internal/obj/arm/obj5.go
cursym.Func().Args = p.To.Val.(int32) /* * find leaf subroutines */ for p := cursym.Func().Text; p != nil; p = p.Link { switch p.As { case obj.ATEXT: p.Mark |= LEAF case ADIV, ADIVU, AMOD, AMODU: cursym.Func().Text.Mark &^= LEAF case ABL, ABX, obj.ADUFFZERO, obj.ADUFFCOPY: cursym.Func().Text.Mark &^= LEAF } } var q2 *obj.Prog
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 21.4K bytes - Viewed (0) -
src/cmd/internal/obj/arm/a.out.go
AFMULSF AFMULSD AFNMULSF AFNMULSD ADIVF ADIVD ASQRTF ASQRTD AABSF AABSD ANEGF ANEGD ASRL ASRA ASLL AMULU ADIVU AMUL AMMUL ADIV AMOD AMODU ADIVHW ADIVUHW AMOVB AMOVBS AMOVBU AMOVH AMOVHS AMOVHU AMOVW AMOVM ASWPBU ASWPW ARFE ASWI AMULA AMULS AMMULA
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 05 16:22:12 UTC 2021 - 7K bytes - Viewed (0)