_Assert
	_Trace
)

var predeclaredFuncs = [...]struct {
	name     string
	nargs    int
	variadic bool
	kind     exprKind
}{
	_Append:  {"append", 1, true, expression},
	_Cap:     {"cap", 1, false, expression},
	_Clear:   {"clear", 1, false, statement},
	_Close:   {"close", 1, false, statement},
	_Complex: {"complex", 2, false, expression},
	_Copy:    {"copy", 2, false, statement},

// initialized.
var HWCap uint

// HWCAP bits. These are exposed by the Linux kernel 5.4.
const (
	// CPU features
	hwcap_MIPS_MSA = 1 << 1
)

func doinit() {
	options = []option{
		{Name: "msa", Feature: &MIPS64X.HasMSA},
	}

	// HWCAP feature bits
	MIPS64X.HasMSA = isSet(HWCap, hwcap_MIPS_MSA)
}

func isSet(hwc uint, value uint) bool {

		{Name: "v7atomics", Feature: &ARM.HasV7Atomics},
	}

	// HWCAP feature bits
	ARM.HasVFPv4 = isSet(HWCap, hwcap_VFPv4)
	ARM.HasIDIVA = isSet(HWCap, hwcap_IDIVA)
	// lpae is required to make the 64-bit instructions LDRD and STRD (and variants) atomic.
	// See ARMv7 manual section B1.6.
	// We also need at least a v7 chip, for the DMB instruction.
	ARM.HasV7Atomics = isSet(HWCap, hwcap_LPAE) && isV7(Platform)
}

        }

        ArtifactTransferEvent event = wrap(transferEvent);
        event.setDataBuffer(buffer);
        event.setDataOffset(0);
        event.setDataLength(length);
        event.setTransferredBytes(transferred);

        listener.transferProgress(event);
    }

    public void transferStarted(TransferEvent transferEvent) {
        listener.transferStarted(wrap(transferEvent));
    }

        .addEqualityGroup(
            LENGTH_EQUIVALENCE.wrap("hello"),
            LENGTH_EQUIVALENCE.wrap("hello"),
            LENGTH_EQUIVALENCE.wrap("world"))
        .addEqualityGroup(LENGTH_EQUIVALENCE.wrap("hi"), LENGTH_EQUIVALENCE.wrap("yo"))
        .addEqualityGroup(
            LENGTH_EQUIVALENCE.<@Nullable String>wrap(null),
            LENGTH_EQUIVALENCE.<@Nullable String>wrap(null))

					seq := wrap(words, max)

					// Compute score for seq.
					start := 0
					score := int64(0)
					if len(seq) == 0 {
						t.Fatalf("wrap seq is empty")
					}
					if seq[0] != 0 {
						t.Fatalf("wrap seq does not start with 0")
					}
					for _, n := range seq[1:] {
						if n <= start {
							t.Fatalf("wrap seq is non-increasing: %v", seq)
						}

	OAND:              "&",
	OAPPEND:           "append",
	OAS:               "=",
	OAS2:              "=",
	OBREAK:            "break",
	OCALL:             "function call", // not actual syntax
	OCAP:              "cap",
	OCASE:             "case",
	OCLEAR:            "clear",
	OCLOSE:            "close",
	OCOMPLEX:          "complex",
	OBITNOT:           "^",
	OCONTINUE:         "continue",
	OCOPY:             "copy",

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                </mxCell>
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                    <mxGeometry x="-60" y="-540" width="330" height="260" as="geometry"/>
                </mxCell>
                <mxCell id="6" value="" style="rounded=0;whiteSpace=wrap;html=1;fontStyle=1;strokeWidth=4;fillColor=#dae8fc;strokeColor=#6c8ebf;" parent="1" vertex="1">

		notOK()
		println(desc, "=", base, len, cap, "want panic")
		return
	}
	if cap != 0 && base != uintptr(xbase) || base >= 10 || len != uintptr(xlen) || cap != uintptr(xcap) {
		notOK()
		if cap == 0 {
			println(desc, "=", base, len, cap, "want", "0-9", xlen, xcap)
		} else {
			println(desc, "=", base, len, cap, "want", xbase, xlen, xcap)
		}
	}
}