(ADD x (SRA y z)) => (ADDshiftRAreg x y z)
(ADC x (SLLconst [c] y) flags) => (ADCshiftLL x y [c] flags)
(ADC x (SRLconst [c] y) flags) => (ADCshiftRL x y [c] flags)
(ADC x (SRAconst [c] y) flags) => (ADCshiftRA x y [c] flags)
(ADC x (SLL y z) flags) => (ADCshiftLLreg x y z flags)
(ADC x (SRL y z) flags) => (ADCshiftRLreg x y z flags)
(ADC x (SRA y z) flags) => (ADCshiftRAreg x y z flags)

	SWI $SYS___clock_gettime50

	MOVW 8(R13), R0 // sec.low
	MOVW 12(R13), R4 // sec.high
	MOVW 16(R13), R2 // nsec

	MOVW $1000000000, R3
	MULLU R0, R3, (R1, R0)
	MUL R3, R4
	ADD.S R2, R0
	ADC R4, R1

	MOVW R0, ret_lo+0(FP)
	MOVW R1, ret_hi+4(FP)
	RET

TEXT runtime·getcontext(SB),NOSPLIT|NOFRAME,$0
	MOVW ctxt+0(FP), R0	// arg 1 - context
	SWI $SYS_getcontext

	XTN2:      "XTN2",
	YIELD:     "YIELD",
	ZIP1:      "ZIP1",
	ZIP2:      "ZIP2",
}

var instFormats = [...]instFormat{
	// ADC <Wd>, <Wn>, <Wm>
	{0xffe0fc00, 0x1a000000, ADC, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},
	// ADC <Xd>, <Xn>, <Xm>
	{0xffe0fc00, 0x9a000000, ADC, instArgs{arg_Xd, arg_Xn, arg_Xm}, nil},
	// ADCS <Wd>, <Wn>, <Wm>
	{0xffe0fc00, 0x3a000000, ADCS, instArgs{arg_Wd, arg_Wn, arg_Wm}, nil},

	ACRC32CH
	ACRC32CW
	ACRC32CX
	ACRC32H
	ACRC32W
	ACRC32X
	ACSEL
	ACSELW
	ACSET
	ACSETM
	ACSETMW
	ACSETW
	ACSINC
	ACSINCW
	ACSINV
	ACSINVW
	ACSNEG
	ACSNEGW
	ADC
	ADCPS1
	ADCPS2
	ADCPS3
	ADMB
	ADRPS
	ADSB
	ADWORD
	AEON
	AEONW
	AEOR
	AEORW
	AERET
	AEXTR
	AEXTRW
	AFABSD
	AFABSS
	AFADDD
	AFADDS
	AFCCMPD

fallback:
	MOVW	$SYS_clock_gettime, R7
	SWI	$0

finish:
	MOVW	sec-12(SP), R0  // sec
	MOVW	nsec-8(SP), R2  // nsec

	MOVW	$1000000000, R3
	MULLU	R0, R3, (R1, R0)
	ADD.S	R2, R0
	ADC	$0, R1	// Add carry bit to upper half.

	MOVW	R0, ret_lo+0(FP)
	MOVW	R1, ret_hi+4(FP)

	RET

// int32 futex(int32 *uaddr, int32 op, int32 val,
//	struct timespec *timeout, int32 *uaddr2, int32 val2);

		var as2 obj.As
		switch p.As {
		case AADD, ASUB, AORR, AEOR, ABIC:
			as2 = p.As // ADD, SUB, ORR, EOR, BIC
		case ARSB:
			as2 = AADD // RSB -> RSB/ADD pair
		case AADC:
			as2 = AADD // ADC -> ADC/ADD pair
		case ASBC:
			as2 = ASUB // SBC -> SBC/SUB pair
		case ARSC:
			as2 = AADD // RSC -> RSC/ADD pair
		default:
			c.ctxt.Diag("unknown second op for %v", p)
		}

#include "../../../../../runtime/textflag.h"

TEXT asmtest(SB),DUPOK|NOSPLIT,$-8

	AND $(1<<63), R1                           // AND $-9223372036854775808, R1     // 21004192
	ADCW ZR, R8, R10                           // 0a011f1a
	ADC R0, R2, R12                            // 4c00009a
	ADCSW R9, R21, R6                          // a602093a
	ADCS R23, R22, R22                         // d60217ba
	ADDW R5.UXTH, R8, R9                       // 0921250b

	hasLock := false
	if lockIndex >= 0 && inst.Prefix[lockIndex]&PrefixImplicit == 0 {
		switch inst.Op {
		// TODO(rsc): Perhaps this instruction class should be derived from the CSV.
		case ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCHG8B, CMPXCHG16B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, XCHG:
			if isMem(inst.Args[0]) {
				hasLock = true
				break
			}
			fallthrough
		default:

		// binary ops
		{name: "ADCSflags", argLength: 3, reg: gp2flags1flags, typ: "(UInt64,Flags)", asm: "ADCS", commutative: true}, // arg0+arg1+carry, set flags.
		{name: "ADCzerocarry", argLength: 1, reg: gp0flags1, typ: "UInt64", asm: "ADC"},                               // ZR+ZR+carry
		{name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true},                                         // arg0 + arg1

[{"Name":"ADC","Bits":"0|0|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADC <Wd>, <Wn>, <Wm>","Code":"","Alias":""},
{"Name":"ADC","Bits":"1|0|0|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"ADC <Xd>, <Xn>, <Xm>","Code":"","Alias":""},
{"Name":"ADCS","Bits":"0|0|1|1|1|0|1|0|0|0|0|Rm:5|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ADCS <Wd>, <Wn>, <Wm>","Code":"","Alias":""},