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  1. okhttp/src/test/java/okhttp3/internal/cache/DiskLruCacheTest.kt

        setUp(parameters.first, parameters.second)
        set("a", "a1", "a2")
        set("b", "b1", "b2")
        set("c", "c1", "c2")
        val iterator = cache.snapshots()
        assertThat(iterator.hasNext()).isTrue()
        iterator.next().use {
          assertThat(it.key()).isEqualTo("a")
          it.assertValue(0, "a1")
          it.assertValue(1, "a2")
        }
        assertThat(iterator.hasNext()).isTrue()
    Registered: Fri Nov 01 11:42:11 UTC 2024
    - Last Modified: Mon Apr 15 14:55:09 UTC 2024
    - 75.8K bytes
    - Viewed (0)
  2. compat/maven-compat/src/test/java/org/apache/maven/repository/metadata/DefaultClasspathTransformationTestType.java

            graph = new MetadataGraph(4, 3);
            /*
             *       v2
             *   v1<
             *       v3-v4
             *
             */
            v1 = graph.addVertex(new ArtifactMetadata("g", "a1", "1.0"));
            graph.setEntry(v1);
            v2 = graph.addVertex(new ArtifactMetadata("g", "a2", "1.0"));
            v3 = graph.addVertex(new ArtifactMetadata("g", "a3", "1.0"));
    Registered: Sun Nov 03 03:35:11 UTC 2024
    - Last Modified: Fri Oct 25 12:31:46 UTC 2024
    - 4.7K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/amd64dynlinkerror.s

    // license that can be found in the LICENSE file.
    
    // Test to make sure that if we use R15 after it is clobbered by
    // a global variable access while dynamic linking, we get an error.
    // See issue 43661.
    
    TEXT ·a1(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    	MOVL $0, R15
    	RET
    TEXT ·a2(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    	MOVQ $0, R15
    	RET
    TEXT ·a3(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Wed Mar 15 20:45:41 UTC 2023
    - 4.8K bytes
    - Viewed (0)
  4. compat/maven-compat/src/test/java/org/apache/maven/repository/metadata/DefaultGraphConflictResolverTest.java

            /*
             *       v2
             *   v1<
             *      v3-v4
             *
             */
            graph = new MetadataGraph(4, 3);
            v1 = graph.addVertex(new ArtifactMetadata("g", "a1", "1.0"));
            graph.setEntry(v1);
            v2 = graph.addVertex(new ArtifactMetadata("g", "a2", "1.0"));
            v3 = graph.addVertex(new ArtifactMetadata("g", "a3", "1.0"));
    Registered: Sun Nov 03 03:35:11 UTC 2024
    - Last Modified: Fri Oct 25 12:31:46 UTC 2024
    - 8.1K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/operand_test.go

    	{"-24(RSP)", "-24(RSP)"},
    	{"$24(RSP)", "$24(RSP)"},
    	{"-32(RSP)", "-32(RSP)"},
    	{"$48", "$48"},
    	{"$(-64*1024)(R7)", "$-65536(R7)"},
    	{"$(8-1)", "$7"},
    	{"a+0(FP)", "a(FP)"},
    	{"a1+8(FP)", "a1+8(FP)"},
    	{"·AddInt32(SB)", `pkg.AddInt32(SB)`},
    	{"runtime·divWVW(SB)", "runtime.divWVW(SB)"},
    	{"$argframe+0(FP)", "$argframe(FP)"},
    	{"$asmcgocall<>(SB)", "$asmcgocall<>(SB)"},
    	{"EQ", "EQ"},
    	{"F29", "F29"},
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Tue Aug 29 18:31:05 UTC 2023
    - 23.9K bytes
    - Viewed (0)
  6. tests/preload_test.go

    	}
    
    	DB.Migrator().DropTable(&Org{}, &EmbeddedAddress{}, &Country{})
    	DB.AutoMigrate(&Org{}, &EmbeddedAddress{}, &Country{})
    
    	org := Org{
    		PostalAddress:   EmbeddedAddress{Name: "a1", Country: &Country{Name: "c1"}},
    		VisitingAddress: EmbeddedAddress{Name: "a2", Country: &Country{Name: "c2"}},
    		Address:         &EmbeddedAddress{Name: "a3", Country: &Country{Name: "c3"}},
    		NestedAddress: NestedAddress{
    Registered: Sun Nov 03 09:35:10 UTC 2024
    - Last Modified: Wed Jun 12 10:00:47 UTC 2024
    - 15.9K bytes
    - Viewed (0)
  7. android/guava-tests/test/com/google/common/collect/MultimapsTest.java

              }
            };
        ListMultimap<String, String> transformed = Multimaps.transformEntries(multimap, transformer);
        assertEquals(ImmutableListMultimap.of("a", "a1", "a", "a4", "a", "a4", "b", "b6"), transformed);
        assertEquals("{a=[a1, a4, a4], b=[b6]}", transformed.toString());
      }
    
      @J2ktIncompatible // Synchronized
      public void testSynchronizedMultimapSampleCodeCompilation() {
    Registered: Fri Nov 01 12:43:10 UTC 2024
    - Last Modified: Wed Oct 30 16:15:19 UTC 2024
    - 38.4K bytes
    - Viewed (0)
  8. okhttp/src/test/java/okhttp3/CacheTest.kt

      @Test
      fun conditionalHitHeadersCombined() {
        server.enqueue(
          MockResponse.Builder()
            .addHeader("Etag", "a")
            .addHeader("Cache-Control: max-age=0")
            .addHeader("A: a1")
            .addHeader("B: b2")
            .addHeader("B: b3")
            .body("abcd")
            .build(),
        )
        server.enqueue(
          MockResponse.Builder()
    Registered: Fri Nov 01 11:42:11 UTC 2024
    - Last Modified: Wed Apr 10 19:46:48 UTC 2024
    - 108.6K bytes
    - Viewed (0)
  9. compat/maven-artifact/src/main/java/org/apache/maven/artifact/versioning/ComparableVersion.java

            private final String value;
    
            StringItem(String value, boolean followedByDigit) {
                if (followedByDigit && value.length() == 1) {
                    // a1 = alpha-1, b1 = beta-1, m1 = milestone-1
                    switch (value.charAt(0)) {
                        case 'a':
                            value = "alpha";
                            break;
                        case 'b':
    Registered: Sun Nov 03 03:35:11 UTC 2024
    - Last Modified: Fri Oct 25 12:31:46 UTC 2024
    - 26K bytes
    - Viewed (0)
  10. src/cmd/asm/internal/arch/arch.go

    	register["T0"] = riscv.REG_T0
    	register["T1"] = riscv.REG_T1
    	register["T2"] = riscv.REG_T2
    	register["S0"] = riscv.REG_S0
    	register["S1"] = riscv.REG_S1
    	register["A0"] = riscv.REG_A0
    	register["A1"] = riscv.REG_A1
    	register["A2"] = riscv.REG_A2
    	register["A3"] = riscv.REG_A3
    	register["A4"] = riscv.REG_A4
    	register["A5"] = riscv.REG_A5
    	register["A6"] = riscv.REG_A6
    	register["A7"] = riscv.REG_A7
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Thu Oct 24 12:32:56 UTC 2024
    - 21.5K bytes
    - Viewed (0)
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