}

	case FST, FSTP, FISTTP, FIST, FISTP, FBSTP:
		if len(args) == 1 {
			args = append(args, "st0")
		}

	case FLD, FXCH, FCOM, FCOMP, FIADD, FIMUL, FICOM, FICOMP, FISUBR, FIDIV, FUCOM, FUCOMP, FILD, FBLD, FADD, FMUL, FSUB, FSUBR, FISUB, FDIV, FDIVR, FIDIVR:
		if len(args) == 1 {
			args = []string{"st0", args[0]}
		}

	case MASKMOVDQU, MASKMOVQ, XLATB, OUTSB, OUTSW, OUTSD:
	FixSegment:

	// special case Pow(-0, y) = +Inf for finite y < 0 and not an odd integer
	FIDBR	$5, F2, F4		//F2 translate to integer F4
	FCMPU	F2, F4
	BNE	zeroNotOdd			// y is not an (odd) integer and y < 0
	FMOVD	$(2.0), F4
	FDIV	F4, F2			// F2 = F2 / 2.0
	FIDBR	$5, F2, F4		//F2 translate to integer F4
	FCMPU	F2, F4
	BNE	negZeroOddInt		// y is an odd integer and y < 0
	BR	zeroNotOdd			// y is not an (odd) integer and y < 0

negZeroGtZero:

	WFMADB	V1, V4, V3, V4
	FMOVD	280(R5), F3
	WFMADB	V1, V2, V3, V2
	FMOVD	272(R5), F3
	WFMADB	V1, V4, V3, V4
L9:
	FMOVD	264(R5), F3
	FMUL	F4, F6
	FMOVD	256(R5), F4
	WFMADB	V1, V4, V3, V4
	FDIV	F6, F2
	LGDR	F4, R1
	FSUB	F3, F4
	FMOVD	248(R5), F6
	WFMSDB	V4, V6, V1, V4
	FMOVD	240(R5), F1
	FMOVD	232(R5), F6
	WFMADB	V4, V6, V1, V6
	FMOVD	224(R5), F1
	FMOVD	216(R5), F3
	WFMADB	V4, V3, V1, V3

	// FDIV <Sd>, <Sn>, <Sm>
	{0xffe0fc00, 0x1e201800, FDIV, instArgs{arg_Sd, arg_Sn, arg_Sm}, nil},
	// FDIV <Dd>, <Dn>, <Dm>
	{0xffe0fc00, 0x1e601800, FDIV, instArgs{arg_Dd, arg_Dn, arg_Dm}, nil},
	// FDIV <Vd>.<t>, <Vn>.<t>, <Vm>.<t>

	FMULSCC F1, F2, F3              // ec620073
	FDIV F1, F2                     // fc420824
	FDIV F1, F2, F3                 // fc620824
	FDIVCC F1, F2, F3               // fc620825
	FDIVS F1, F2                    // ec420824
	FDIVS F1, F2, F3                // ec620824
	FDIVSCC F1, F2, F3              // ec620825
	FTDIV F1, F2, $2                // fd011100
	FTSQRT F1, $2	                // fd000940

	FSUBS	F2, F13                // b30b00d2
	FSUB	F3, F12                // b31b00c3
	FMULS	F4, F11                // b31700b4
	FMUL	F5, F10                // b31c00a5
	FDIVS	F6, F9                 // b30d0096
	FDIV	F7, F8                 // b31d0087
	FABS	F1, F2                 // b3100021
	FSQRTS	F3, F4                 // b3140043
	FSQRT	F5, F15                // b31500f5
	FIEBR	$0, F0, F1             // b3570010

		args[0], args[1] = args[1], args[0]
		fallthrough

	case FCMP, FCMPE:
		if _, ok := inst.Args[1].(Imm); ok {
			args[1] = "$(0.0)"
		}
		fallthrough

	case FADD, FSUB, FMUL, FNMUL, FDIV, FMAX, FMIN, FMAXNM, FMINNM, FCSEL, FMADD, FMSUB, FNMADD, FNMSUB:
		if strings.HasSuffix(op, "MADD") || strings.HasSuffix(op, "MSUB") {
			args[2], args[3] = args[3], args[2]
		}
		if r, ok := inst.Args[0].(Reg); ok {

		{name: "POPCNTB", argLength: 1, reg: gp11, asm: "POPCNTB"}, // number of set bits in each byte of arg0 placed in corresponding byte

		{name: "FDIV", argLength: 2, reg: fp21, asm: "FDIV"},   // arg0/arg1
		{name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS"}, // arg0/arg1

		{name: "DIVD", argLength: 2, reg: gp21, asm: "DIVD", typ: "Int64"},   // arg0/arg1 (signed 64-bit)

		{name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS", resultInArg0: true},                                                   // fp32 arg0 / arg1
		{name: "FDIV", argLength: 2, reg: fp21, asm: "FDIV", resultInArg0: true},                                                     // fp64 arg0 / arg1

	FCOS:            "FCOS",
	FDECSTP:         "FDECSTP",
	FDIV:            "FDIV",
	FDIVP:           "FDIVP",
	FDIVR:           "FDIVR",
	FDIVRP:          "FDIVRP",
	FFREE:           "FFREE",
	FFREEP:          "FFREEP",
	FIADD:           "FIADD",
	FICOM:           "FICOM",
	FICOMP:          "FICOMP",
	FIDIV:           "FIDIV",
	FIDIVR:          "FIDIVR",
	FILD:            "FILD",