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Results 1 - 10 of 107 for instructions (0.16 sec)

  1. src/cmd/asm/internal/arch/arch.go

    	instructions["JZ"] = x86.AJEQ   /* alternate */
    	instructions["MASKMOVDQU"] = x86.AMASKMOVOU
    	instructions["MOVD"] = x86.AMOVQ
    	instructions["MOVDQ2Q"] = x86.AMOVQ
    	instructions["MOVNTDQ"] = x86.AMOVNTO
    	instructions["MOVOA"] = x86.AMOVO
    	instructions["PSLLDQ"] = x86.APSLLO
    	instructions["PSRLDQ"] = x86.APSRLO
    	instructions["PADDD"] = x86.APADDL
    	// Spellings originally used in CL 97235.
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Thu Oct 24 12:32:56 UTC 2024
    - 21.5K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/riscv64.s

    	// NOT pseudo-instruction
    	NOT	X5					// 93c2f2ff
    	NOT	X5, X6					// 13c3f2ff
    
    	// NEG/NEGW pseudo-instructions
    	NEG	X5					// b3025040
    	NEG	X5, X6					// 33035040
    	NEGW	X5					// bb025040
    	NEGW	X5, X6					// 3b035040
    
    	// This jumps to the second instruction in the function (the
    	// first instruction is an invisible stack pointer adjustment).
    	JMP	start					// JMP	2
    
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Fri Oct 25 12:05:29 UTC 2024
    - 16.8K bytes
    - Viewed (0)
  3. doc/asm.html

    Function is the outermost frame of the call stack. Traceback should stop at this function.
    </li>
    </ul>
    
    <h3 id="special-instructions">Special instructions</h3>
    
    <p>
    The <code>PCALIGN</code> pseudo-instruction is used to indicate that the next instruction should be aligned
    to a specified boundary by padding with no-op instructions.
    </p>
    
    <p>
    It is currently supported on arm64, amd64, ppc64, loong64 and riscv64.
    
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Tue Nov 28 19:15:27 UTC 2023
    - 36.3K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/arch/arm.go

    // one of the comparison instructions that require special handling.
    func IsARMCMP(op obj.As) bool {
    	switch op {
    	case arm.ACMN, arm.ACMP, arm.ATEQ, arm.ATST:
    		return true
    	}
    	return false
    }
    
    // IsARMSTREX reports whether the op (as defined by an arm.A* constant) is
    // one of the STREX-like instructions that require special handling.
    func IsARMSTREX(op obj.As) bool {
    	switch op {
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Wed Oct 23 15:18:14 UTC 2024
    - 6.1K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/amd64error.s

    	// CLWB instructions:
    	CLWB BX                          // ERROR "invalid instruction"
    	// CLDEMOTE instructions:
    	CLDEMOTE BX                      // ERROR "invalid instruction"
    	// WAITPKG instructions:
    	TPAUSE (BX)                      // ERROR "invalid instruction"
    	UMONITOR (BX)                    // ERROR "invalid instruction"
    	UMWAIT (BX)                      // ERROR "invalid instruction"
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Wed Jun 14 00:03:57 UTC 2023
    - 8.9K bytes
    - Viewed (0)
  6. src/cmd/asm/internal/arch/arm64.go

    // one of the comparison instructions that require special handling.
    func IsARM64ADR(op obj.As) bool {
    	switch op {
    	case arm64.AADR, arm64.AADRP:
    		return true
    	}
    	return false
    }
    
    // IsARM64CMP reports whether the op (as defined by an arm64.A* constant) is
    // one of the comparison instructions that require special handling.
    func IsARM64CMP(op obj.As) bool {
    	switch op {
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Thu Sep 29 09:04:58 UTC 2022
    - 10.4K bytes
    - Viewed (0)
  7. src/cmd/asm/internal/arch/loong64.go

    		return true
    	}
    	return false
    }
    
    // IsLoong64MUL reports whether the op (as defined by an loong64.A* constant) is
    // one of the MUL/DIV/REM instructions that require special handling.
    func IsLoong64MUL(op obj.As) bool {
    	switch op {
    	case loong64.AMUL, loong64.AMULU, loong64.AMULV, loong64.AMULVU,
    		loong64.ADIV, loong64.ADIVU, loong64.ADIVV, loong64.ADIVVU,
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Mon Jul 29 02:47:00 UTC 2024
    - 1.8K bytes
    - Viewed (0)
  8. src/cmd/asm/internal/arch/ppc64.go

    // one of the CMP instructions that require special handling.
    func IsPPC64CMP(op obj.As) bool {
    	switch op {
    	case ppc64.ACMP, ppc64.ACMPU, ppc64.ACMPW, ppc64.ACMPWU, ppc64.AFCMPO, ppc64.AFCMPU:
    		return true
    	}
    	return false
    }
    
    // IsPPC64NEG reports whether the op (as defined by an ppc64.A* constant) is
    // one of the NEG-like instructions that require special handling.
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Fri May 17 21:53:50 UTC 2024
    - 2.2K bytes
    - Viewed (0)
  9. README.md

    After downloading a binary release, visit https://go.dev/doc/install
    for installation instructions.
    
    #### Install From Source
    
    If a binary distribution is not available for your combination of
    operating system and architecture, visit
    https://go.dev/doc/install/source
    for source installation instructions.
    
    ### Contributing
    
    Go is the work of thousands of contributors. We appreciate your help!
    
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Mon Jul 22 17:45:27 UTC 2024
    - 1.4K bytes
    - Viewed (0)
  10. src/cmd/asm/internal/arch/mips.go

    // one of the CMP instructions that require special handling.
    func IsMIPSCMP(op obj.As) bool {
    	switch op {
    	case mips.ACMPEQF, mips.ACMPEQD, mips.ACMPGEF, mips.ACMPGED,
    		mips.ACMPGTF, mips.ACMPGTD:
    		return true
    	}
    	return false
    }
    
    // IsMIPSMUL reports whether the op (as defined by an mips.A* constant) is
    // one of the MUL/DIV/REM/MADD/MSUB instructions that require special handling.
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Wed Mar 04 19:06:44 UTC 2020
    - 1.7K bytes
    - Viewed (0)
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