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Results 1 - 10 of 22 for R5 (0.04 sec)

  1. src/cmd/asm/internal/asm/testdata/loong64enc6.s

    TEXT asmtest(SB),DUPOK|NOSPLIT,$0
    	// MOVWP LOREG_64(Rx), Ry
    	MOVWP	81985529216486896(R4), R5	// 9e571315dec3b703feac6816de4b000384f8100085000025
    	MOVWP	-81985529216486896(R4), R5	// 7ea8ec14de4388031e539717deb73f0384f8100085000025
    	MOVWP	R4, 81985529216486896(R5)	// 9e571315dec3b703feac6816de4b0003a5f81000a4000025
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Tue Oct 28 01:21:57 UTC 2025
    - 609 bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/ppc64.s

    	MOVDBR (R3)(R0), R5             // 7ca01c28
    	MOVDBR (R3), R5                 // 7ca01c28
    	MOVWBR (R3)(R4), R5             // 7ca41c2c
    	MOVWBR (R3)(R0), R5             // 7ca01c2c
    	MOVWBR (R3), R5                 // 7ca01c2c
    	MOVHBR (R3)(R4), R5             // 7ca41e2c
    	MOVHBR (R3)(R0), R5             // 7ca01e2c
    	MOVHBR (R3), R5                 // 7ca01e2c
    	OR $0, R0, R0
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Thu Nov 21 18:27:17 UTC 2024
    - 51.7K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/loong64enc4.s

    	ADDV    $0x27312345fffff800, R4, R5     // ADDV	$2824077224892692480, R4, R5    // 1e00a002be682416decf090385f81000
    	AND     $0x27312345fffff800, R4         // AND	$2824077224892692480, R4        // 1e00a002be682416decf090384f81400
    	AND     $0x27312345fffff800, R4, R5     // AND	$2824077224892692480, R4, R5    // 1e00a002be682416decf090385f81400
    
    	// ADDV/AND C_DCON32_0, [r1], r2
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Thu Feb 20 14:31:35 UTC 2025
    - 3.2K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/arm64error.s

    	ADDS	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    	ADDSW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    	SUB	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    	SUBW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Tue Oct 14 19:00:00 UTC 2025
    - 38.4K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/arm.s

    	SRA	$14, R5              // 4557a0e1
    	SRA	$15, R5              // c557a0e1
    	SRA	$30, R5              // 455fa0e1
    	SRA	$31, R5              // c55fa0e1
    	SRA.S	$14, R5              // 4557b0e1
    	SRA.S	$15, R5              // c557b0e1
    	SRA.S	$30, R5              // 455fb0e1
    	SRA.S	$31, R5              // c55fb0e1
    	SRA	R5, R6, R7           // 5675a0e1
    	SRA.S	R5, R6, R7           // 5675b0e1
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Fri Dec 15 20:51:01 UTC 2023
    - 69K bytes
    - Viewed (0)
  6. src/cmd/asm/internal/asm/testdata/loong64enc5.s

    	ADDV	$0xfedcba9876543210, R5, R4	// ADDV	$-81985529216486896, R5, R4	// 7ea8ec14de4388031e539717deb73f03a4f81000
    	ADDV	$0x4edcba9876543210, R4		// ADDV	$5682621993817747984, R4	// 7ea8ec14de4388031e539717deb7130384f81000
    	ADDV	$0x4edcba9876543210, R5, R4	// ADDV	$5682621993817747984, R5, R4	// 7ea8ec14de4388031e539717deb71303a4f81000
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Fri May 16 05:00:16 UTC 2025
    - 1.5K bytes
    - Viewed (0)
  7. src/cmd/asm/internal/asm/testdata/loong64enc3.s

    	ADD	$74565, R4, R5			// 5e020014de178d0385781000
    	ADD	$4097, R4, R5  			// 3e000014de07800385781000
    	ADDW	$74565, R4, R5			// 5e020014de178d0385781000
    	ADDW	$4097, R4, R5  			// 3e000014de07800385781000
    	ADDV	$74565, R4, R5			// 5e020014de178d0385f81000
    	ADDV	$4097, R4, R5 			// 3e000014de07800385f81000
    	AND	$74565, R4, R5			// 5e020014de178d0385f81400
    	AND	$4097, R4, R5			// 3e000014de07800385f81400
    
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Thu Nov 27 00:46:52 UTC 2025
    - 11.2K bytes
    - Viewed (0)
  8. src/cmd/asm/internal/asm/testdata/loong64enc2.s

    	ADDW	$65536, R4, R5		// 1e02001485781000
    	ADDW	$4096, R4, R5		// 3e00001485781000
    	ADDW	$65536, R4		// 1e02001484781000
    	ADDW	$4096, R4		// 3e00001484781000
    	ADDV	$65536, R4, R5		// 1e02001485f81000
    	ADDV	$4096, R4, R5		// 3e00001485f81000
    	ADDV	$65536, R4		// 1e02001484f81000
    	ADDV	$4096, R4		// 3e00001484f81000
    	AND	$65536, R4, R5		// 1e02001485f81400
    	AND	$4096, R4, R5		// 3e00001485f81400
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Thu Nov 27 00:46:52 UTC 2025
    - 5.6K bytes
    - Viewed (0)
  9. src/cmd/asm/internal/asm/testdata/arm64.s

    	SWPLD	R5, (RSP), R7                        // e78365f8
    	SWPLW	R5, (R6), R7                         // c78065b8
    	SWPLW	R5, (RSP), R7                        // e78365b8
    	SWPLH	R5, (R6), R7                         // c7806578
    	SWPLH	R5, (RSP), R7                        // e7836578
    	SWPLB	R5, (R6), R7                         // c7806538
    	SWPLB	R5, (RSP), R7                        // e7836538
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Mon Nov 10 17:34:13 UTC 2025
    - 96.1K bytes
    - Viewed (0)
  10. src/cmd/asm/internal/asm/testdata/loong64enc1.s

    	SUB	R4, R5			// a5101100
    	SUBW	R4, R5			// a5101100
    	SUBV	R4, R5			// a5901100
    	ADD	R4, R5			// a5101000
    	ADDW	R4, R5			// a5101000
    	ADDV	R4, R5			// a5901000
    	AND	R4, R5			// a5901400
    	NEGW	R4, R5			// 05101100
    	NEGV	R4, R5			// 05901100
    	SLL	R4, R5			// a5101700
    	SLL	R4, R5, R6		// a6101700
    	SRL	R4, R5			// a5901700
    	SRL	R4, R5, R6	 	// a6901700
    	SRA	R4, R5			// a5101800
    	SRA	R4, R5, R6	 	// a6101800
    	ROTR	R4, R5			// a5101b00
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Thu Nov 27 00:46:52 UTC 2025
    - 44.5K bytes
    - Viewed (0)
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