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Results 1 - 10 of 11 for HMUL (0.05 sec)
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src/cmd/compile/internal/test/fixedbugs_test.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Feb 06 18:07:35 UTC 2023 - 2.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/config.go
useSSE bool // Use SSE for non-float operations useAvg bool // Use optimizations that need Avg* operations useHmul bool // Use optimizations that need Hmul* operations SoftFloat bool // Race bool // race detector enabled BigEndian bool // UseFMA bool // Use hardware FMA operation
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 02 16:11:47 UTC 2024 - 12.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64.rules
(Select0 (Mul32uover x y)) => (Select0 <typ.UInt32> (MULLU x y)) (Select1 (Mul(64|32)uover x y)) => (SETO (Select1 <types.TypeFlags> (MUL(Q|L)U x y))) (Hmul(64|32) ...) => (HMUL(Q|L) ...) (Hmul(64|32)u ...) => (HMUL(Q|L)U ...) (Div(64|32|16) [a] x y) => (Select0 (DIV(Q|L|W) [a] x y)) (Div8 x y) => (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y))) (Div(64|32|16)u x y) => (Select0 (DIV(Q|L|W)U x y))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
src/cmd/compile/internal/x86/ssa.go
n.To.Reg = x86.REG_DX } j.To.SetTarget(n) j2.To.SetTarget(s.Pc()) } case ssa.Op386HMULL, ssa.Op386HMULLU: // the frontend rewrites constant division by 8/16/32 bit integers into // HMUL by a constant // SSA rewrites generate the 64 bit versions // Arg[0] is already in AX as it's the only register we allow // and DX is the only output we care about (the high bits) p := s.Prog(v.Op.Asm())
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 01:26:58 UTC 2023 - 26.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARMOps.go
{name: "RSBconst", argLength: 1, reg: gp11, asm: "RSB", aux: "Int32"}, // auxInt - arg0 {name: "MUL", argLength: 2, reg: gp21, asm: "MUL", commutative: true}, // arg0 * arg1 {name: "HMUL", argLength: 2, reg: gp21, asm: "MULL", commutative: true}, // (arg0 * arg1) >> 32, signed {name: "HMULU", argLength: 2, reg: gp21, asm: "MULLU", commutative: true}, // (arg0 * arg1) >> 32, unsigned
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 41K bytes - Viewed (0) -
src/runtime/race/testdata/mop_test.go
y = z ch <- 1 }() <-ch <-ch } func TestRaceDivConst(t *testing.T) { var x, y, z uint32 _ = x ch := make(chan int, 2) go func() { x = y / 3 // involves only a HMUL node ch <- 1 }() go func() { y = z ch <- 1 }() <-ch <-ch } func TestRaceMod(t *testing.T) { var x, y, z int _ = x ch := make(chan int, 2) go func() {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 23 16:46:25 UTC 2023 - 28.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS.rules
(Select1 (Sub32carry <t> x y)) => (SGTU <typ.Bool> (SUB <t.FieldType(0)> x y) x) (Sub32withcarry <t> x y c) => (SUB (SUB <t> x y) c) (Mul(32|16|8) ...) => (MUL ...) (Mul(32|64)F ...) => (MUL(F|D) ...) (Hmul(32|32u) x y) => (Select0 (MUL(T|TU) x y)) (Mul32uhilo ...) => (MULTU ...) (Div32 x y) => (Select1 (DIV x y)) (Div32u x y) => (Select1 (DIVU x y)) (Div16 x y) => (Select1 (DIV (SignExt16to32 x) (SignExt16to32 y)))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 35.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(Div16u x y) => (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y)) (Div8 x y) => (DIVW (SignExt8to32 x) (SignExt8to32 y)) (Div8u x y) => (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y)) (Hmul(64|64u|32|32u) ...) => (MULH(D|DU|W|WU) ...) (Mul(32|64)F ...) => ((FMULS|FMUL) ...) (Div(32|64)F ...) => ((FDIVS|FDIV) ...) // Lowering float <=> int
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390X.rules
(Div16 x y) => (DIVW (MOVHreg x) (MOVHreg y)) (Div16u x y) => (DIVWU (MOVHZreg x) (MOVHZreg y)) (Div8 x y) => (DIVW (MOVBreg x) (MOVBreg y)) (Div8u x y) => (DIVWU (MOVBZreg x) (MOVBZreg y)) (Hmul(64|64u) ...) => (MULH(D|DU) ...) (Hmul32 x y) => (SRDconst [32] (MULLD (MOVWreg x) (MOVWreg y))) (Hmul32u x y) => (SRDconst [32] (MULLD (MOVWZreg x) (MOVWZreg y))) (Mod64 x y) => (MODD x y) (Mod64u ...) => (MODDU ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 74.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM.rules
(Sub(Ptr|32|16|8) ...) => (SUB ...) (Sub(32|64)F ...) => (SUB(F|D) ...) (Sub32carry ...) => (SUBS ...) (Sub32withcarry ...) => (SBC ...) (Mul(32|16|8) ...) => (MUL ...) (Mul(32|64)F ...) => (MUL(F|D) ...) (Hmul(32|32u) ...) => (HMU(L|LU) ...) (Mul32uhilo ...) => (MULLU ...) (Div32 x y) => (SUB (XOR <typ.UInt32> // negate the result if one operand is negative
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 90.1K bytes - Viewed (0)