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Results 1 - 10 of 34 for BP (0.03 sec)
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src/cmd/asm/internal/asm/testdata/avx512enc/avx512_ifma.s
VPMADD52HUQ X0, X11, K1, X18 // 62e2a509b5d0 VPMADD52HUQ 17(SP)(BP*2), X11, K1, X18 // 62e2a509b5946c11000000 VPMADD52HUQ -7(DI)(R8*4), X11, K1, X18 // 62a2a509b59487f9ffffff VPMADD52HUQ X7, X31, K1, X18 // 62e28501b5d7 VPMADD52HUQ X0, X31, K1, X18 // 62e28501b5d0 VPMADD52HUQ 17(SP)(BP*2), X31, K1, X18 // 62e28501b5946c11000000
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue May 22 14:57:15 UTC 2018 - 13.2K bytes - Viewed (0) -
internal/bpool/bpool.go
func (bp *BytePoolCap) Populate() { for _, buf := range reedsolomon.AllocAligned(cap(bp.c), bp.wcap) { bp.Put(buf[:bp.w]) } } // Get gets a []byte from the BytePool, or creates a new one if none are // available in the pool. func (bp *BytePoolCap) Get() (b []byte) { if bp == nil { return nil } select { case b = <-bp.c: // reuse existing buffer default:
Registered: Sun Nov 03 19:28:11 UTC 2024 - Last Modified: Thu Aug 29 01:40:52 UTC 2024 - 3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/avx512enc/avx512f.s
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue May 22 14:57:15 UTC 2018 - 410.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/avx512enc/avx512pf.s
VGATHERPF0QPS K2, (BP)(Z10*2) // 62b27d4ac74c5500 VGATHERPF0QPS K2, (R10)(Z29*8) // 62927d42c70cea VGATHERPF0QPS K2, (R14)(Z29*8) // 62927d42c70cee VGATHERPF1DPD K2, (R14)(Y29*8) // 6292fd42c614ee VGATHERPF1DPD K2, (AX)(Y4*1) // 62f2fd4ac61420 VGATHERPF1DPD K2, (BP)(Y10*2) // 62b2fd4ac6545500
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue May 22 14:57:15 UTC 2018 - 3.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64error.s
VPGATHERQQ (BP)(X2*2), K1, X2 // ERROR "index and destination registers should be distinct" VPGATHERQQ (BP)(Y15*2), K1, Y15 // ERROR "index and destination registers should be distinct" VPGATHERQQ (BP)(Z20*2), K1, Z20 // ERROR "index and destination registers should be distinct" VPGATHERDQ (BP)(X2*2), K1, X2 // ERROR "index and destination registers should be distinct"
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Wed Jun 14 00:03:57 UTC 2023 - 8.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/avx512enc/avx512cd.s
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue May 22 14:57:15 UTC 2018 - 12.9K bytes - Viewed (0) -
internal/bpool/bpool_test.go
bp.Put(make([]byte, bp.w, bp.wcap+1)) // wrong capacity is rejected (more) bp.Put(make([]byte, width)) // wrong capacity is rejected (very less) if len(bp.c) > 0 { t.Fatal("bytepool should have rejected invalid packets") } // Try putting a short slice into pool bp.Put(make([]byte, bp.w, bp.wcap)[:2]) if len(bp.c) != 1 { t.Fatal("bytepool should have accepted short slice with sufficient capacity") }
Registered: Sun Nov 03 19:28:11 UTC 2024 - Last Modified: Thu Aug 29 01:40:52 UTC 2024 - 2.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/avx512enc/avx512_vbmi.s
VPERMB 17(SP)(BP*1), Y31, K7, Y22 // 62e205278db42c11000000 VPERMB -7(CX)(DX*8), Y31, K7, Y22 // 62e205278db4d1f9ffffff VPERMB Y5, Y5, K7, Y22 // 62e2552f8df5 VPERMB Y19, Y5, K7, Y22 // 62a2552f8df3 VPERMB Y31, Y5, K7, Y22 // 6282552f8df7
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue May 22 14:57:15 UTC 2018 - 28.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/avx512enc/avx512_vnni.s
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue May 22 14:57:15 UTC 2018 - 27.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/avx512enc/avx512dq.s
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue May 22 14:57:15 UTC 2018 - 194.8K bytes - Viewed (0)