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Results 101 - 110 of 159 for reg1 (3.41 sec)
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src/cmd/compile/internal/ssa/_gen/main.go
} if v.reg.clobbers > 0 { fmt.Fprintf(w, "clobbers: %d,%s\n", v.reg.clobbers, a.regMaskComment(v.reg.clobbers)) } // reg outputs s = s[:0] for i, r := range v.reg.outputs { s = append(s, intPair{countRegs(r), i}) } if len(s) > 0 { sort.Sort(byKey(s)) fmt.Fprintln(w, "outputs: []outputInfo{") for _, p := range s { r := v.reg.outputs[p.val]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Jan 19 22:42:34 UTC 2023 - 16.9K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/a.out.go
// SYSREG_END is the last item in the automatically generated system register // declaration, and it is defined in the sysRegEnc.go file. // Define the special register after REG_SPECIAL, the first value of it should be // REG_{name} = SYSREG_END + iota. const ( REG_SPECIAL = obj.RBaseARM64 + 1<<12 ) // Register assignments: // // compiler allocates R0 up as temps // compiler allocates register variables R7-R25
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 18 17:56:30 UTC 2023 - 18.1K bytes - Viewed (0) -
src/cmd/internal/obj/x86/a.out.go
REGCTXT = REG_DX REGENTRYTMP0 = REG_R12 // scratch register available at function entry in ABIInternal REGENTRYTMP1 = REG_R13 // scratch register available at function entry in ABIInternal REGG = REG_R14 // g register in ABIInternal REGEXT = REG_R15 // compiler allocates external registers R15 down FREGMIN = REG_X0 + 5 // first register variable
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 31 20:28:39 UTC 2021 - 6.8K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/a.out.go
C_AND0CON C_ADDCON // -0x800 <= v < 0 C_ANDCON // 0 < v <= 0xFFF C_LCON // other 32 C_DCON // other 64 (could subdivide further) C_SACON // $n(REG) where n <= int12 C_SECON C_LACON // $n(REG) where int12 < n <= int32 C_LECON C_DACON // $n(REG) where int32 < n C_STCON // $tlsvar C_SBRA C_LBRA C_SAUTO C_LAUTO C_SEXT C_LEXT C_ZOREG C_SOREG C_LOREG C_GOK
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 5.7K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arm.go
return true } return false } // IsARMBFX reports whether the op (as defined by an arm.A* constant) is one the // BFX-like instructions which are in the form of "op $width, $LSB, (Reg,) Reg". func IsARMBFX(op obj.As) bool { switch op { case arm.ABFX, arm.ABFXU, arm.ABFC, arm.ABFI: return true } return false }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Nov 18 17:59:44 UTC 2022 - 6.1K bytes - Viewed (0) -
src/cmd/compile/internal/x86/ssa.go
p := s.Prog(x86.AADDL) p.From.Type = obj.TYPE_REG p.To.Type = obj.TYPE_REG p.To.Reg = v.Reg() p.From.Reg = v.Args[1].Reg() p = s.Prog(x86.ARCRL) p.From.Type = obj.TYPE_CONST p.From.Offset = 1 p.To.Type = obj.TYPE_REG p.To.Reg = v.Reg() case ssa.Op386ADDLconst: r := v.Reg() a := v.Args[0].Reg() if r == a { if v.AuxInt == 1 { p := s.Prog(x86.AINCL)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 01:26:58 UTC 2023 - 26.7K bytes - Viewed (0) -
src/runtime/memclr_ppc64x.s
zero512setup: // setup for dcbz loop CMP R4, $512 // check if at least 512 BLT remain SRD $9, R4, R8 // loop count for 512 chunks MOVD R8, CTR // set up counter MOVD $128, R9 // index regs for 128 bytes MOVD $256, R10 MOVD $384, R11 PCALIGN $16 zero512: DCBZ (R3+R0) // clear first chunk DCBZ (R3+R9) // clear second chunk DCBZ (R3+R10) // clear third chunk
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 16 17:08:59 UTC 2023 - 4.4K bytes - Viewed (0) -
pilot/pkg/xds/eds_sh_test.go
memRegistry.XdsUpdater = server.Discovery memRegistry.ClusterID = clusterID reg := serviceregistry.Simple{ ClusterID: clusterID, ProviderID: provider.Mock, DiscoveryController: memRegistry, } server.Env().ServiceDiscovery.(*aggregate.Controller).AddRegistry(reg) gws := make([]*meshconfig.Network_IstioNetworkGateway, 0) for _, gatewayIP := range gatewaysIP {
Registered: Fri Jun 14 15:00:06 UTC 2024 - Last Modified: Fri Jan 12 18:20:36 UTC 2024 - 10.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/parse.go
// Expect (SB), (FP), (PC), or (SP) p.get('(') reg := p.get(scanner.Ident).String() p.get(')') p.setPseudoRegister(a, reg, isStatic, prefix) } // setPseudoRegister sets the NAME field of addr for a pseudo-register reference such as (SB). func (p *Parser) setPseudoRegister(addr *obj.Addr, reg string, isStatic bool, prefix rune) { if addr.Reg != 0 { p.errorf("internal error: reg %s already set in pseudo", reg) } switch reg {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Feb 21 14:34:57 UTC 2024 - 36.9K bytes - Viewed (0) -
src/runtime/mfinal.go
continue } argRegs = intArgRegs unlock(&finlock) if raceenabled { racefingo() } for fb != nil { for i := fb.cnt; i > 0; i-- { f := &fb.fin[i-1] var regs abi.RegArgs // The args may be passed in registers or on stack. Even for // the register case, we still need the spill slots. // TODO: revisit if we remove spill slots. //
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 01:56:56 UTC 2024 - 19K bytes - Viewed (0)