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Results 21 - 30 of 32 for Add1 (0.04 sec)
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tensorflow/compiler/mlir/tensorflow/tests/tensor_array_ops_decomposition.mlir
// CHECK: %[[ADD1:.*]] = "tf.AddV2"(%[[OLD_SLICE1]], %[[UPDATE_SLICE1]]) // CHECK: %[[UPDATE1:.*]] = "tf.XlaDynamicUpdateSlice"(%[[UPDATE0]], %[[ADD1]] // CHECK-SAME: (tensor<5x3xf32>, tensor<1x3xf32>, tensor<2xi32>) -> tensor<5x3xf32> // CHECK: "tf.AssignVariableOp"(%[[VAR]], %[[UPDATE1]])
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 49K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/canonicalize.mlir
%4 = "tf.Log"(%3) {device = "/job:localhost/replica:0/task:0/device:GPU:0"}: (tensor<4x4xf32>) -> tensor<4x4xf32> // CHECK: %[[ADD1:.*]] = "tf.AddV2" // CHECK: %[[LOG1:.*]] = "tf.Log"(%[[ADD1]]) %5 = "tf.AddV2"(%4, %1): (tensor<4x4xf32>, tensor<1xf32>) -> tensor<4x4xf32> %6 = "tf.Log"(%5): (tensor<4x4xf32>) -> tensor<4x4xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 09 22:07:10 UTC 2024 - 132.1K bytes - Viewed (0) -
platforms/core-configuration/file-collections/src/test/groovy/org/gradle/api/internal/file/collections/DefaultConfigurableFileCollectionSpec.groovy
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Mon Mar 18 17:09:50 UTC 2024 - 53K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/prepare-tf.mlir
// CHECK-DAG: %[[CONSTANT1:.*]] = arith.constant dense<0.000000e+00> : tensor<4xf32> // variance + epsilon // CHECK: %[[ADD1:.*]] = "tf.Add"(%[[ARG4:.*]], %[[CONSTANT]]) // rsqrt(variance + epsilon) // CHECK: %[[RSQRT:.*]] = "tf.Rsqrt"(%[[ADD1]]) // scale * rsqrt(variance + epsilon) // CHECK: %[[MUL1:.*]] = "tf.Mul"(%[[ARG1:.*]], %[[RSQRT]])
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed May 29 07:26:59 UTC 2024 - 59.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/transforms/tf_passes.td
%island1:3 = tf_executor.island { %add1 = "tf.Add"(%arg0, %arg1) : (tensor<*xi32>, tensor<i32>) -> tensor<*xi32> %add2 = "tf.Add"(%add1, %arg1) : (tensor<*xi32>, tensor<i32>) -> tensor<*xi32> %res = "tf.Print"(%add2) { message = "add result" } : (tensor<*xi32>) -> (tensor<*xi32>) tf_executor.yield %add1, %add2 : tensor<*xi32>, tensor<*xi32> }
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Jun 12 21:18:05 UTC 2024 - 99.6K bytes - Viewed (0) -
tensorflow/compiler/mlir/g3doc/_includes/tf_passes.md
%island1:3 = tf_executor.island { %add1 = "tf.Add"(%arg0, %arg1) : (tensor<*xi32>, tensor<i32>) -> tensor<*xi32> %add2 = "tf.Add"(%add1, %arg1) : (tensor<*xi32>, tensor<i32>) -> tensor<*xi32> %res = "tf.Print"(%add2) { message = "add result" } : (tensor<*xi32>) -> (tensor<*xi32>) tf_executor.yield %add1, %add2 : tensor<*xi32>, tensor<*xi32> }
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Aug 02 02:26:39 UTC 2023 - 96.4K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/optimize.mlir
// Fusing: %[[add:[0-9].*]] = tfl.add %arg0, %arg1 {fused_activation_function = "NONE"} : tensor<1xf32> // Fusing: %[[add1:[0-9].*]] = tfl.add %arg0, %[[add]] {fused_activation_function = "RELU"} : tensor<1xf32> // Fusing: %[[relu:[0-9].*]] = "tfl.relu"(%arg0) : (tensor<1xf32>) -> tensor<1xf32> // Fusing: %[[add2:[0-9].*]] = tfl.add %[[relu]], %[[add1]] {fused_activation_function = "RELU6"} : tensor<1xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 16 20:31:41 UTC 2024 - 284.1K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/tf-ops.mlir
}, { ^bb0(%barg0: tensor<*xf32>, %barg1: tensor<i32>): %add0 = "tf.Add"(%barg0, %barg0) : (tensor<*xf32>, tensor<*xf32>) -> tensor<*xf32> %add1 = "tf.Add"(%barg1, %barg1) : (tensor<i32>, tensor<i32>) -> tensor<i32> "tf.Yield"(%add0, %add1) : (tensor<*xf32>, tensor<i32>) -> () }) { is_stateless = false } : (tensor<*xf32>, tensor<i32>) -> (tensor<*xf32>, tensor<i32>) func.return %0#0 : tensor<*xf32> }
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 23 14:40:35 UTC 2023 - 236.4K bytes - Viewed (0) -
src/vendor/golang.org/x/crypto/chacha20poly1305/chacha20poly1305_amd64.s
openAVX2Tail128LoopB: ADDQ $16, itr2 chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) VPALIGNR $4, BB1, BB1, BB1 VPALIGNR $8, CC1, CC1, CC1 VPALIGNR $12, DD1, DD1, DD1 chachaQR_AVX2(AA1, BB1, CC1, DD1, TT0) VPALIGNR $12, BB1, BB1, BB1 VPALIGNR $8, CC1, CC1, CC1 VPALIGNR $4, DD1, DD1, DD1 CMPQ itr2, itr1 JB openAVX2Tail128LoopA CMPQ itr2, $160 JNE openAVX2Tail128LoopB
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 29 21:28:33 UTC 2023 - 105.6K bytes - Viewed (0) -
tensorflow/compiler/mlir/tf2xla/tests/legalize-tf.mlir
// CHECK-DAG: %[[ADD1:.*]] = chlo.broadcast_add %[[FEATURES]], %[[ONE]] {broadcast_dimensions = array<i64>} // CHECK-DAG: %[[MULGRAD:.*]] = mhlo.multiply %[[GRADIENTS]], %[[ADD1]] : (tensor<4x8xf32>, tensor<?x?xf32>) -> tensor<4x8xf32> // CHECK: %[[RESULT:.*]] = mhlo.select %[[PRED]], %[[GRADIENTS]], %[[MULGRAD]]
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon May 06 18:46:23 UTC 2024 - 335.5K bytes - Viewed (0)