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Results 1 - 8 of 8 for MUL (0.04 sec)

  1. tensorflow/compiler/mlir/lite/experimental/tac/execution_metadata_exporter_test.cc

      %0 = "tfl.add"(%arg0, %arg1) {fused_activation_function = "RELU6",  per_device_costs = {CPU = 5.0 : f32, GPU = 1.0 : f32}, tac.device = "GPU"} : (tensor<1xf32>, tensor<1xf32>) -> tensor<1xf32>
      %1 = "tfl.mul"(%0, %arg2) {fused_activation_function = "RELU6", per_device_costs = {CPU = 5.0 : f32, GPU = 1.0 : f32}, tac.device = "GPU"} : (tensor<1xf32>, tensor<1xf32>) -> tensor<1xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Jun 11 06:11:34 UTC 2024
    - 6K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/PPC64.rules

    (Mod32u x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLW y (DIVWU x y)))
    
    // (x + y) / 2 with x>=y => (x - y) / 2 + y
    (Avg64u <t> x y) => (ADD (SRDconst <t> (SUB <t> x y) [1]) y)
    
    (Mul64 ...) => (MULLD ...)
    (Mul(32|16|8) ...) => (MULLW ...)
    (Select0 (Mul64uhilo x y)) => (MULHDU x y)
    (Select1 (Mul64uhilo x y)) => (MULLD x y)
    
    (Div64 [false] x y) => (DIVD x y)
    (Div64u ...) => (DIVDU ...)
    (Div32 [false] x y) => (DIVW x y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 53.2K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssagen/ssa.go

    			loopHead := s.f.NewBlock(ssa.BlockPlain)
    			loopBody := s.f.NewBlock(ssa.BlockPlain)
    
    			// Pick right size ops.
    			var mul, and, add, zext ssa.Op
    			if s.config.PtrSize == 4 {
    				mul = ssa.OpMul32
    				and = ssa.OpAnd32
    				add = ssa.OpAdd32
    				zext = ssa.OpCopy
    			} else {
    				mul = ssa.OpMul64
    				and = ssa.OpAnd64
    				add = ssa.OpAdd64
    				zext = ssa.OpZeroExt32to64
    			}
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jun 10 19:44:43 UTC 2024
    - 284.9K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/tensorflow/transforms/tf_passes.td

            %add_out, %add_control = tf_executor.island wraps "tf.Add"(%arg2, %arg3) : (tensor<f32>, tensor<f32>) -> tensor<f32>
            %mul_out, %mul_control = tf_executor.island wraps "tf.Mul"(%arg2, %arg3) : (tensor<f32>, tensor<f32>) -> tensor<f32>
            %barrier = tf_executor.island(%assign_0_control, %assign_1_control, %add_control, %mul_control) wraps "tf.NoOp"() : () -> ()
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Jun 12 21:18:05 UTC 2024
    - 99.6K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/tensorflow/ir/tf_generated_ops.td

      }];
    
      let arguments = (ins
        TF_FpOrI32OrI64Tensor:$input,
    
        I64Attr:$group_size,
        I64Attr:$group_key,
        I64Attr:$instance_key,
        TF_AnyStrAttrOf<["Min", "Max", "Mul", "Add"]>:$merge_op,
        TF_AnyStrAttrOf<["Id", "Div"]>:$final_op,
        I64ArrayAttr:$subdiv_offsets,
        DefaultValuedOptionalAttr<I64ArrayAttr, "{}">:$wait_for,
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Jun 11 23:24:08 UTC 2024
    - 793K bytes
    - Viewed (0)
  6. RELEASE.md

        *   Unary GPU kernels: Abs, Atanh, Acos, Acosh, Asin, Asinh, Atan, Cos, Cosh, Sin, Sinh, Tan, Tanh.
        *   Binary GPU kernels: AddV2, Sub, Div, DivNoNan, Mul, MulNoNan, FloorDiv, Equal, NotEqual, Greater, GreaterEqual, LessEqual, Less.
    
    * `tf.lite`
        * Add experimental supports conversion of models that may be larger than 2GB before buffer deduplication
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Jun 11 23:24:08 UTC 2024
    - 730.3K bytes
    - Viewed (0)
  7. pkg/printers/internalversion/printers_test.go

    			expected: []metav1.TableRow{{Cells: []interface{}{"test5", "LoadBalancer", "10.9.8.7", "3.4.5.6,80.11.12.10", "8888/tcp", "<unknown>"}}},
    		},
    		{
    			// Test LoadBalancer service with mul ExternalIPs
    			service: api.Service{
    				ObjectMeta: metav1.ObjectMeta{Name: "test6"},
    				Spec: api.ServiceSpec{
    					Type: api.ServiceTypeLoadBalancer,
    					Ports: []api.ServicePort{
    						{
    Registered: Sat Jun 15 01:39:40 UTC 2024
    - Last Modified: Tue Jun 11 14:04:15 UTC 2024
    - 218.6K bytes
    - Viewed (0)
  8. tensorflow/compiler/mlir/tf2xla/transforms/legalize_tf.cc

        StringRef reduce_op = op.getReduceOp();
        if (reduce_op == "Add") {
          BuildReduceBody<AddOp>(element_type, &reduce_scatter.getComputation(),
                                 &rewriter);
        } else if (reduce_op == "Mul") {
          BuildReduceBody<MulOp>(element_type, &reduce_scatter.getComputation(),
                                 &rewriter);
        } else if (reduce_op == "Min") {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Jun 11 20:00:43 UTC 2024
    - 291.8K bytes
    - Viewed (0)
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