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Results 1 - 10 of 29 for maskOf (0.33 sec)
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src/cmd/compile/internal/ssa/rewrite.go
// Rewrite mask to apply after the final left shift. mask_3 := (mask_1 & mask_2) << uint(GetPPC64Shiftsh(sld)) r_1 := 32 - srw r_2 := GetPPC64Shiftsh(sld) r_3 := (r_1 + r_2) & 31 // This can wrap. if uint64(uint32(mask_3)) != mask_3 || mask_3 == 0 { return 0 } return encodePPC64RotateMask(int64(r_3), int64(mask_3), 32) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 64.2K bytes - Viewed (0) -
staging/src/k8s.io/apiserver/pkg/server/options/encryptionconfig/config_test.go
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Thu May 16 16:56:39 UTC 2024 - 72.3K bytes - Viewed (0) -
src/net/netip/netip_test.go
masked: Prefix{}, }, } for _, test := range tests { t.Run(test.prefix.String(), func(t *testing.T) { got := test.prefix.Masked() if got != test.masked { t.Errorf("Masked=%s, want %s", got, test.masked) } }) } } func TestPrefix(t *testing.T) { tests := []struct { prefix string ip Addr bits int str string
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Jun 04 17:10:01 UTC 2024 - 54.3K bytes - Viewed (0) -
src/runtime/mbitmap.go
// the address of the first word referenced by mask. addr uintptr // mask is a bitmask where each bit corresponds to pointer-words after addr. // Bit 0 is the pointer-word at addr, Bit 1 is the next word, and so on. // If a bit is 1, then there is a pointer at that word. // nextFast and next mask out bits in this mask as their pointers are processed. mask uintptr
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 00:18:55 UTC 2024 - 60K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/regalloc.go
} // allocReg chooses a register from the set of registers in mask. // If there is no unused register, a Value will be kicked out of // a register to make room. func (s *regAllocState) allocReg(mask regMask, v *Value) register { if v.OnWasmStack { return noRegister } mask &= s.allocatable mask &^= s.nospill if mask == 0 { s.f.Fatalf("no register available for %s", v.LongString()) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 17:49:56 UTC 2023 - 87.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/transforms/prepare_tf.cc
padded_val.push_back(padding_val[i]); if (mask) *mask |= 1 << i; } } LogicalResult matchAndRewrite(Operation *op, PatternRewriter &rewriter) const override { TF::StridedSliceOp strided_slice_op = llvm::cast<TF::StridedSliceOp>(op); // Handle ellipsis mask. if (strided_slice_op.getEllipsisMask() != 0) {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue May 28 21:49:50 UTC 2024 - 64.6K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/sys/unix/syscall_linux.go
//sys fanotifyMark(fd int, flags uint, mask uint64, dirFd int, pathname *byte) (err error) func FanotifyMark(fd int, flags uint, mask uint64, dirFd int, pathname string) (err error) { if pathname == "" { return fanotifyMark(fd, flags, mask, dirFd, nil) } p, err := BytePtrFromString(pathname) if err != nil { return err } return fanotifyMark(fd, flags, mask, dirFd, p) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 05:26:45 UTC 2024 - 77.5K bytes - Viewed (0) -
cmd/peer-rest-server.go
} pattern := event.NewPattern(prefix, suffix) var eventNames []event.Name var mask pubsub.Mask for _, ev := range values[peerRESTListenEvents] { eventName, err := event.ParseName(ev) if err != nil { return grid.NewRemoteErr(err) } mask.MergeMaskable(eventName) eventNames = append(eventNames, eventName) }
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Fri May 24 23:05:23 UTC 2024 - 52.1K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/sys/windows/syscall_windows.go
func (b PSAPI_WORKING_SET_EX_BLOCK) intField(start, length int) uint64 { var mask PSAPI_WORKING_SET_EX_BLOCK for pos := start; pos < start+length; pos++ { mask |= (1 << pos) } masked := b & mask return uint64(masked >> start) } // PSAPI_WORKING_SET_EX_INFORMATION contains extended working set information for a process.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 05 22:18:42 UTC 2024 - 82.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390X.rules
// is valid to merge the shift mask (^(uint64(0)<<c)) into the selected // bits mask (i.e. that the resultant mask is non-zero and contiguous). // (RISBGZ (SLDconst x [c]) {r}) && r.InMerge(^uint64(0)<<c) != nil => (RISBGZ x {(*r.InMerge(^uint64(0)<<c)).RotateLeft(c)}) (RISBGZ (SRDconst x [c]) {r}) && r.InMerge(^uint64(0)>>c) != nil => (RISBGZ x {(*r.InMerge(^uint64(0)>>c)).RotateLeft(-c)})
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 74.3K bytes - Viewed (0)