Search Options

Results per page
Sort
Preferred Languages
Advance

Results 11 - 20 of 114 for i64 (0.02 sec)

  1. tensorflow/compiler/mlir/quantization/stablehlo/tests/pipelines/process_nchw_tensor.mlir

    // CHECK: %[[ADD:.+]] = stablehlo.add %[[CONV]], %[[BIAS_CONST]] : tensor<1x5x5x4xf32>
    // CHECK: %[[REDUCE_WINDOW_MAX:.+]] = "stablehlo.reduce_window"(%[[ADD]], %[[INIT_VALUE_CONST:.+]])
    // CHECK: <{window_dimensions = array<i64: 1, 2, 2, 1>, window_strides = array<i64: 1, 2, 2, 1>}>
    // CHECK: stablehlo.maximum
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Apr 18 20:32:46 UTC 2024
    - 12.6K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/tensorflow/tests/embedding_pipelining.mlir

        "tf.AssignAddVariableOp"(%37, %cst_12) {_has_manual_control_dependencies = true, _replication_info = "while/cluster_while_body_451", _xla_compile_device_type = "TPU", device = ""} : (tensor<*x!tf_type.resource<tensor<i64>>>, tensor<i64>) -> ()
    
        return %res_n, %arg1 : tensor<i32>, tensor<*x!tf_type.resource<tensor<i64>>>
      }
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 33.1K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/tensorflow/tests/replicate_to_island.mlir

                tf_device.return %5: tensor<i64>
              }) {device = "/TPU:2"} : () -> (tensor<i64>)
              tf_device.return %4 : tensor<i64>
            }) : () -> (tensor<i32>, tensor<i64>)
            tf_device.return %3#0, %3#1 : tensor<i32>, tensor<i64>
          }
          tf_executor.yield %2#0, %2#1, %2#2, %2#3 : tensor<i32>, tensor<i32>, tensor<i64>, tensor<i64>
        }
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Oct 31 08:59:10 UTC 2023
    - 15.1K bytes
    - Viewed (0)
  4. src/cmd/link/internal/wasm/asm.go

    	"runtime.gcWriteBarrier7": {Results: []byte{I64}},                                     // -> bufptr
    	"runtime.gcWriteBarrier8": {Results: []byte{I64}},                                     // -> bufptr
    	"cmpbody":                 {Params: []byte{I64, I64, I64, I64}, Results: []byte{I64}}, // a, alen, b, blen -> -1/0/1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jan 22 16:17:48 UTC 2024
    - 21.9K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/tfrt/tests/sink_in_invariant_ops.mlir

      %1 = "tf.BatchFunction"(%arg0, %0) {allowed_batch_sizes = [6], batch_timeout_micros = 100000 : i64, batching_queue = "", container = "", device = "/device:CPU:0", enable_large_batch_splitting = false, f = @batched_function, max_batch_size = 6 : i64, max_enqueued_batches = 10 : i64, num_batch_threads = 1 : i64, operandSegmentSizes = array<i32: 1, 1>, shared_name = "batch/"} : (tensor<1x3xf32>, tensor<!tf_type.resource<tensor<1x3xf32>>>) -> tensor<*xf32>...
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 21K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/tfrt/tests/hoist_invariant_ops.mlir

    "tf.BatchFunction"(%cst) <{allowed_batch_sizes = [1], batch_timeout_micros = 5000 : i64, batching_queue = "", container = "", enable_large_batch_splitting = true, f = @_batched, low_priority_allowed_batch_sizes = [], low_priority_batch_timeout_micros = 0 : i64, low_priority_max_batch_size = 0 : i64, low_priority_max_enqueued_batches = 0 : i64, max_batch_size = 1 : i64, max_enqueued_batches = 1 : i64, num_batch_threads = 1 : i64, operandSegmentSizes = array<i32: 1, 0>, shared_name = "batch_function___inf...
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Apr 01 23:54:14 UTC 2024
    - 18.3K bytes
    - Viewed (0)
  7. tensorflow/compiler/mlir/quantization/stablehlo/tests/bridge/optimize.mlir

          dim_numbers = [b, 0, 1, f]x[0, 1, i, o]->[b, 0, 1, f],
          window = {stride = [1, 1], pad = [[0, 0], [0, 0]],
          lhs_dilate = [1, 1], rhs_dilate = [1, 1]}
          {batch_group_count = 1 : i64, feature_group_count = 1 : i64}
        : (tensor<?x3x2x1xi8>, tensor<2x1x1x1xi8>) -> tensor<?x2x2x1xi32>
      %1 = chlo.broadcast_add %0, %zp_offset : (
          tensor<?x2x2x1xi32>, tensor<?x2x2x1xi32>) -> tensor<?x2x2x1xi32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sat Feb 24 02:26:47 UTC 2024
    - 10.7K bytes
    - Viewed (0)
  8. tensorflow/compiler/mlir/tensorflow/tests/update_control_dependencies.mlir

        %control_11 = tf_executor.island wraps "tf.LoadTPUEmbeddingAdagradParameters"(%outputs_2, %outputs_5) {config = "", num_shards = 1 : i64, shard_id = 0 : i64, table_id = -1 : i64, table_name = "table4"} : (tensor<8xf32>, tensor<8xf32>) -> ()
        tf_executor.fetch
      }
      return
    }
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri Nov 03 18:12:49 UTC 2023
    - 25.2K bytes
    - Viewed (0)
  9. tensorflow/compiler/mlir/tensorflow/tests/tpu_validate_inputs.mlir

        // expected-error @+1 {{'tf.TPUPartitionedInput' op TF2XLA TPU bridge input check: number of inputs inconsistent. num_cores_per_replica=2 no. of inputs=3}}
        %pi, %c0 = tf_executor.island wraps "tf.TPUPartitionedInput"(%arg0, %arg1, %arg1) {index = 1 : i64} : (tensor<i32>, tensor<i32>, tensor<i32>) -> tensor<i32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue May 07 06:51:01 UTC 2024
    - 15.7K bytes
    - Viewed (0)
  10. tensorflow/compiler/mlir/quantization/tensorflow/tests/quantize_composite_functions_drq.mlir

    // CHECK-LABEL: func private @quantized_matmul_fn_0
    // CHECK:  %0 = "tf.UniformQuantizedDotHybrid"(%arg0, %arg1, %arg2, %arg3)
    // CHECK-SAME: rhs_quantization_axis = -1 : i64
    // CHECK-SAME: rhs_quantization_max_val = 127 : i64
    // CHECK-SAME: rhs_quantization_min_val = -128 : i64
    
    }
    
    // -----
    
    module {
      func.func @conv(%arg0: tensor<1x2x2x3xf32>) -> (tensor<*xf32>, tensor<*xf32>) {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri Jan 05 18:35:42 UTC 2024
    - 9.8K bytes
    - Viewed (0)
Back to top