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Results 61 - 70 of 173 for conv_3d (0.2 sec)

  1. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_gpu_cc_70.mlir

      // cuDNN prefers NCHW data format for spatial convolutions.
      // CHECK: "tf.Conv2D"(%[[INPUT_TRANSPOSE:[0-9]*]], %arg1)
      // CHECK-SAME: data_format = "NCHW"
      %0 = "tf.Conv2D"(%input, %filter)
           {
             data_format = "NHWC",
             padding = "VALID",
             strides = [1, 1, 1, 1]
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Jun 21 08:41:18 UTC 2022
    - 8.5K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/lite/transforms/prepare_tf.cc

          state.padding = rewriter.getStringAttr("VALID");
        }
        auto conv_op = static_cast<const ConcreteType *>(this)->createTFLOp(
            &state, rewriter, op->getLoc(), tf_op.getType(), input, filter, bias);
    
        rewriter.replaceOp(op, conv_op.getResult());
        return success();
      }
    
      const IntegerAttr intAttrOne;
    
     private:
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue May 28 21:49:50 UTC 2024
    - 64.6K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/quantization/tensorflow/tests/quantize_composite_functions_xla.mlir

      }
      func.func private @composite_conv2d_with_bias_and_relu6_fn_1(%arg0: tensor<*xf32>, %arg1: tensor<*xf32>, %arg2: tensor<2xf32>) -> tensor<*xf32> attributes {tf_quant.composite_function} {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Jan 08 01:16:10 UTC 2024
    - 25.2K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/quantization/tensorflow/tests/quantize_composite_functions.mlir

      }
      func.func private @composite_conv2d_with_bias_and_relu6_fn_2(%arg0: tensor<*xf32>, %arg1: tensor<*xf32>, %arg2: tensor<2xf32>) -> tensor<*xf32> attributes {tf_quant.composite_function} {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Nov 06 01:23:21 UTC 2023
    - 15.2K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/lite/transforms/dilated_conv.h

    //
    //
    //   SpaceToBatchND -> Expand -> Conv2D -> Squeeze -> BatchToSpaceND -> BiasAdd
    //
    //   SpaceToBatchND -> Expand -> Conv2D -> Squeeze -> Pad -> BatchToSpaceND ->
    //   BiasAdd
    //
    //   SpaceToBatchND -> Expand -> Conv2D -> Squeeze -> BiasAdd -> BatchToSpaceND
    //
    //   SpaceToBatchND -> Conv2D -> Pad -> BatchToSpaceND -> BiasAdd
    //
    //   SpaceToBatchND -> Conv2D -> BatchToSpaceND -> BiasAdd
    //
    //
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Apr 25 16:01:03 UTC 2024
    - 20K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/quantization/common/quantization_lib/quantization_driver_test.cc

        }
        func.func private @composite_fn_1(%arg0: tensor<1x4x4x3xf32>, %arg1: tensor<3x1x1x3xf32>, %arg2: tensor<3xf32>) -> tensor<1x4x4x3xf32> attributes {tf_quant.composite_function} {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Apr 25 16:01:03 UTC 2024
    - 7.9K bytes
    - Viewed (0)
  7. tensorflow/compiler/mlir/tensorflow/tests/fused_kernel_matcher.mlir

    // RUN: tf-opt %s -tf-fused-kernel-matcher | FileCheck %s
    
    //===----------------------------------------------------------------------===//
    // Conv2D + BiasAdd + <Activation> fusions.
    //===----------------------------------------------------------------------===//
    
    // CHECK-LABEL: conv2DBiasAdd_noActivation
    func.func @conv2DBiasAdd_noActivation(%arg0: tensor<128xf32>, %arg1: tensor<1x1x3x128xf32>, %arg2: tensor<8x32x32x3xf32>) -> (tensor<*xf32>) {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 13.2K bytes
    - Viewed (0)
  8. tensorflow/compiler/mlir/tensorflow/tests/optimize.mlir

      %filter = arith.constant dense<2.0> : tensor<3x3x3x16xf32>
      %bias = arith.constant dense<3.0> : tensor<16xf32>
      %value = arith.constant dense<4.0> : tensor<16xf32>
      %0 = "tf.Conv2D"(%arg, %filter) {T = "tfdtype$DT_FLOAT", data_format = "NHWC", dilations = [1, 2, 3, 1], padding = "SAME", strides = [1, 4, 5, 1]} : (tensor<256x32x32x3xf32>, tensor<3x3x3x16xf32>) -> tensor<256x8x7x16xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri Jan 05 18:35:42 UTC 2024
    - 3.3K bytes
    - Viewed (0)
  9. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_to_nhwc.mlir

      // CHECK: %[[ARG_PERM:.*]] = "tf.Const"() <{value = dense<[0, 2, 3, 1]> : tensor<4xi64>}>
      // CHECK: %[[ARG_TRANSPOSE:[0-9]*]] = "tf.Transpose"(%arg0, %[[ARG_PERM]])
    
      // CHECK: %[[CONV2D:[0-9]*]] = "tf.Conv2D"(%[[ARG_TRANSPOSE]], %arg1)
      // CHECK-SAME: data_format = "NHWC"
      // CHECK-SAME: dilations = [1, 3, 4, 2]
      // CHECK-SAME: explicit_paddings = [1, 2, 5, 6, 7, 8, 3, 4]
      // CHECK-SAME: padding = "EXPLICIT"
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 4.5K bytes
    - Viewed (0)
  10. tensorflow/compiler/jit/tests/keras_imagenet_main.pbtxt

          type: DT_INT32
        }
      }
      attr {
        key: "keep_dims"
        value {
          b: false
        }
      }
    }
    node {
      name: "conv1_1/Conv2D"
      op: "Conv2D"
      input: "conv1_pad_1/Pad"
      input: "conv1_1/Conv2D/Cast"
      device: "/job:localhost/replica:0/task:0/device:GPU:0"
      attr {
        key: "T"
        value {
          type: DT_HALF
        }
      }
      attr {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 30 02:52:54 UTC 2019
    - 1.3M bytes
    - Viewed (0)
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