canUseHeaderValue = false
        } else {
          headerValue = value
        }
      }
      name.equals("Pragma", ignoreCase = true) -> {
        // Might specify additional cache-control params. We invalidate just in case.
        canUseHeaderValue = false
      }
      else -> {
        continue@loop
      }
    }

    var pos = 0
    while (pos < value.length) {
      val tokenStart = pos

        .build()
    val invalidate = client.newCall(request).execute()
    assertThat(invalidate.body.string()).isEqualTo("B")
    assertThat(get(url).body.string()).isEqualTo("C")
  }

  @Test
  fun postInvalidatesCacheWithUncacheableResponse() {
    // 1. Seed the cache.
    // 2. Invalidate it with an uncacheable response.
    // 3. Expect a cache miss.

     * Used in SMB2 READ and WRITE requests to indicate RDMA channel
     */
    public static final int SMB2_CHANNEL_RDMA_V1 = 0x00000001;

    /**
     * SMB2 Channel constant for RDMA V1 invalidate
     * Used to indicate RDMA with invalidation
     */
    public static final int SMB2_CHANNEL_RDMA_V1_INVALIDATE = 0x00000002;

    /**
     * SMB2 RDMA Transform Capabilities negotiate context ID
     */

    }

    /**
     * Encode the JSP content.
     * @param value The value.
     * @return The encoded value.
     */
    public static String encodeJsp(final String value) {
        return value.replace("<% try{ %>", TRY_STATEMENT)
                .replace("<% }catch(Exception e){session.invalidate();} %>", CACHE_AND_SESSION_INVALIDATE_STATEMENT);
    }

        new Receiver<ReferenceEntry<Integer, Integer>>() {
          @Override
          public void accept(ReferenceEntry<Integer, Integer> entry) {
            Integer key = entry.getKey();
            cache.invalidate(key);
          }
        });
  }

  public void testEviction_lru() {
    // test lru within a single segment
    IdentityLoader<Integer> loader = identityLoader();

    }
    
    /**
     * Invalidate this memory region
     */
    public abstract void invalidate();
    
    protected abstract int generateLocalKey();
    protected abstract int generateRemoteKey();
    protected abstract long getBufferAddress(ByteBuffer buffer);
    
    @Override
    public void close() {
        invalidate();
        valid = false;
    }
}
```

            try {
                final StatsObject data = statsCache.getIfPresent(key);
                if (data != null && data.decrement() <= 0) {
                    statsCache.invalidate(key);
                    final Long begin = data.remove(BEGIN_KEY);
                    if (begin != null) {
                        printStats(keyObj, data, begin, true);
                    }
                }

      Key key2 = new Key(2);
      String value2 = key2.toString();
      assertSame(value1, cache.getUnchecked(key1));
      assertSame(value2, cache.getUnchecked(key2));
      cache.invalidate(key1);
      assertFalse(cache.asMap().containsKey(key1));
      assertTrue(cache.asMap().containsKey(key2));
      assertEquals(1, cache.size());
      assertEquals(ImmutableSet.of(key2), cache.asMap().keySet());

        // }

        this.memoryRegister = new Object(); // Placeholder

        log.debug("DiSNI memory region registered, size: {}", buffer.remaining());
    }

    @Override
    public void invalidate() {
        if (valid && memoryRegister != null) {
            try {
                // In real implementation, this would deregister the memory:
                // memoryRegister.deregisterMemory();

            entry.updateState(newState);
            // Flush any cached data if losing write cache
            if (!entry.hasWriteCache()) {
                flushCachedWrites(entry.path);
            }
            // Invalidate cached data if losing read cache
            if (!entry.hasReadCache()) {
                invalidateReadCache(entry.path);
            }
            entry.breaking = false;
        }
    }