ADDW	R1, R2, R3
	ADDW	R1, ZR, R3
	ADD	$1, R2, R3
	ADD	R1, R2, R3
	ADD	R1, ZR, R3
	ADD	$1, R2, R3
	ADDW	$1, R2
	ADDW	R1, R2
	ADD	$1, R2
	ADD	R1, R2
	ADD	R1>>11, R2
	ADD	R1<<22, R2
	ADD	R1->33, R2
	ADD	$0x000aaa, R2, R3               // ADD $2730, R2, R3                      // 43a82a91
	ADD	$0x000aaa, R2                   // ADD $2730, R2                          // 42a82a91

{"Name":"MADD","Bits":"0|0|0|1|1|0|1|1|0|0|0|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"MADD <Wd>, <Wn>, <Wm>, <Wa>","Code":"","Alias":"This instruction is used by the alias MUL."},
{"Name":"MADD","Bits":"1|0|0|1|1|0|1|1|0|0|0|Rm:5|0|Ra:5|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"MADD <Xd>, <Xn>, <Xm>, <Xa>","Code":"","Alias":"This instruction is used by the alias MUL."},

	FMOVD   0(R1), F2
	WFCHDBS V0, V2, V4
	BEQ     L9
	WFCHDBS V2, V0, V2
	BNE     L1
	MOVD    $tanhxmone<>+0(SB), R1
	FMOVD   0(R1), F0
	FMOVD   F0, ret+8(FP)
	RET

L3:
	FADD    F4, F2
	FMOVD   tanhrodataL18<>+80(SB), F4
	FMADD   F4, F2, F0
	FMOVD   tanhrodataL18<>+72(SB), F1
	WFMDB   V0, V0, V3
	FMOVD   tanhrodataL18<>+64(SB), F2
	WFMADB  V0, V1, V2, V1
	FMOVD   tanhrodataL18<>+56(SB), F4

	WORD    $0xA7487FBE     //lhi %r4,32702
	FMADD   F3, F2, F1
	SUBW    R1, R4
	RISBGZ	$57, $60, $3, R4, R12
	WORD    $0x682C5000     //ld %f2,0(%r12,%r5)
	FMSUB   F2, F4, F0
	RISBGN	$0, $15, $48, R1, R2
	WFMADB  V0, V6, V2, V6
	RISBGN	$0, $15, $48, R4, R3
	LDGR    R2, F2
	LDGR    R3, F0
	FMADD   F2, F1, F2
	FMADD   F0, F6, F0
	FADD    F2, F0
	FMOVD   F0, ret+8(FP)
	RET

L22:

	MOVD    $sincoss2<>+0(SB), R2
	FMOVD   0(R2), F7
	WFMADB  V6, V3, V7, V3
	MOVD    $sincoss3<>+0(SB), R2
	FMADD   F5, F4, F0
	FMOVD   0(R2), F4
	MOVD    $sincoss1<>+0(SB), R2
	FMADD   F1, F6, F4
	FMOVD   0(R2), F1
	FMADD   F3, F2, F1
	FMUL    F0, F2
	WFMADB  V6, V4, V1, V6
	TMLL	R1, $2
	FMADD   F6, F2, F0
	BNE     L34
	FMOVD   F0, ret+8(FP)
	RET

L33:
	MOVD    $sincosxnan<>+0(SB), R1

	{AADD, C_BITCON, C_RSP, C_NONE, C_RSP, C_NONE, 62, 8, 0, 0, 0},
	{AADD, C_BITCON, C_NONE, C_NONE, C_RSP, C_NONE, 62, 8, 0, 0, 0},
	{ACMP, C_BITCON, C_RSP, C_NONE, C_NONE, C_NONE, 62, 8, 0, 0, 0},
	{AADD, C_ADDCON2, C_RSP, C_NONE, C_RSP, C_NONE, 48, 8, 0, NOTUSETMP, 0},
	{AADD, C_ADDCON2, C_NONE, C_NONE, C_RSP, C_NONE, 48, 8, 0, NOTUSETMP, 0},
	{AADD, C_MOVCON2, C_RSP, C_NONE, C_RSP, C_NONE, 13, 12, 0, 0, 0},

	WFMADB	V2, V7, V5, V7
	FMOVD	0(R5), F5
	WFMADB	V2, V5, V16, V5
	WFMADB	V1, V4, V3, V4
	WFMADB	V6, V7, V5, V6
	FMUL	F0, F2
	FMADD	F4, F1, F6
	FMADD	F6, F2, F0
	MOVW	R2, R6
	MOVW	R1, R7
	CMPUBLE	R6, R7, L1
	MOVD	$·atanxpim<>+0(SB), R1
	WORD	$0xED801000	//madb	%f0,%f8,0(%r1)
	BYTE	$0x00
	BYTE	$0x1E
L1:
atanIsZero:
	FMOVD	F0, ret+8(FP)

	FMOVD	88(R5), F6
	FMOVD	0(R1), F4
	WFMSDB	V0, V6, V4, V6
	FMOVD	80(R5), F1
	FADD	F6, F4
	FMOVD	72(R5), F2
	FMSUB	F1, F4, F0
	FMOVD	64(R5), F3
	WFMADB	V4, V2, V0, V2
	FMOVD	56(R5), F1
	WFMADB	V4, V3, V2, V4
	FMUL	F2, F2
	VLEG	$0, 48(R5), V18
	LGDR	F6, R1
	FMOVD	40(R5), F5
	FMOVD	32(R5), F3
	FMADD	F1, F2, F3
	FMOVD	24(R5), F1
	FMOVD	16(R5), F7
	FMOVD	8(R5), F0
	WFMADB	V2, V7, V1, V7

	FMOVD	192(R5), F1
	LDGR	R3, F3
	WORD	$0xED221000	//madb %f2,%f2,0(%r2,%r1)
	BYTE	$0x20
	BYTE	$0x1E
	WFMADB	V4, V6, V1, V4
	FMUL	F3, F2
	FMADD	F4, F2, F0
	FMOVD	F0, ret+8(FP)
	RET
L12:
	FMOVD	184(R5), F0
	WFMADB	V6, V0, V6, V0
	FMOVD	F0, ret+8(FP)
	RET
L5:
	FMOVD	176(R5), F1
	FMADD	F0, F0, F1
	FMOVD	168(R5), F3
	WFMDB	V1, V1, V2
	FMOVD	160(R5), F0

# NONE:           %[[add:.*]], %[[add_control:.*]] = tf_executor.island wraps "tf.Add"(%[[ARG_0]], %[[ARG_1]])
# NONE:           fetch %[[add]]

# UNKNOWN-LABEL: func @main
# UNKNOWN-SAME:  (%[[ARG_0:[a-z0-9]+]]: tensor<*xi32>, %[[ARG_1:[a-z0-9]+]]: tensor<*xi32>) -> tensor<*xi32>
# UNKNOWN-SAME:  control_outputs = ""
# UNKNOWN-SAME:  inputs = "input0,input1"
# UNKNOWN-SAME:  outputs = "Add"