register[s] = int16(i + x86.REG_AL)
	}
	// Pseudo-registers.
	register["SB"] = RSB
	register["FP"] = RFP
	register["PC"] = RPC
	if linkArch == &x86.Linkamd64 {
		// Alias g to R14
		register["g"] = x86.REGG
	}
	// Register prefix not used on this architecture.

	instructions := make(map[string]obj.As)
	for i, s := range obj.Anames {
		instructions[s] = obj.As(i)
	}

TEXT errors(SB),$0
	AND	$1, RSP                                          // ERROR "illegal source register"
	ANDS	$1, R0, RSP                                      // ERROR "illegal combination"
	ADDSW	R7->32, R14, R13                                 // ERROR "shift amount out of range 0 to 31"
	ADD	R1.UXTB<<5, R2, R3                               // ERROR "shift amount out of range 0 to 4"

pkg debug/macho, type RegsAMD64 struct, R11 uint64
pkg debug/macho, type RegsAMD64 struct, R12 uint64
pkg debug/macho, type RegsAMD64 struct, R13 uint64
pkg debug/macho, type RegsAMD64 struct, R14 uint64
pkg debug/macho, type RegsAMD64 struct, R15 uint64
pkg debug/macho, type RegsAMD64 struct, R8 uint64
pkg debug/macho, type RegsAMD64 struct, R9 uint64
pkg debug/macho, type RegsAMD64 struct, SI uint64