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Results 21 - 25 of 25 for R14 (2.15 sec)

  1. src/cmd/asm/internal/asm/testdata/amd64enc.s

    	ANDNQ (BX), R14, DX                     // c4e288f213
    	ANDNQ (R11), R14, DX                    // c4c288f213
    	ANDNQ DX, R14, DX                       // c4e288f2d2
    	ANDNQ R11, R14, DX                      // c4c288f2d3
    	ANDNQ (BX), R14, R11                    // c46288f21b
    	ANDNQ (R11), R14, R11                   // c44288f21b
    	ANDNQ DX, R14, R11                      // c46288f2da
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Fri Oct 08 21:38:44 UTC 2021
    - 581.9K bytes
    - Viewed (1)
  2. src/cmd/asm/internal/asm/testdata/amd64enc_extra.s

    	VPEXTRW $127, X20, BP             // 62b17d08c5ec7f or 62e37d0815e57f or 62e3fd0815e57f
    	VPEXTRW $17, X20, R14             // 62317d08c5f411 or 62c37d0815e611 or 62c3fd0815e611
    	VPEXTRW $127, X20, R14            // 62317d08c5f47f or 62c37d0815e67f or 62c3fd0815e67f
    	VPEXTRW $17, X20, (AX)            // 62e37d08152011 or 62e3fd08152011
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Thu Feb 20 11:20:03 UTC 2025
    - 57.7K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/arch/arch.go

    		register[s] = int16(i + x86.REG_AL)
    	}
    	// Pseudo-registers.
    	register["SB"] = RSB
    	register["FP"] = RFP
    	register["PC"] = RPC
    	if linkArch == &x86.Linkamd64 {
    		// Alias g to R14
    		register["g"] = x86.REGG
    	}
    	// Register prefix not used on this architecture.
    
    	instructions := make(map[string]obj.As)
    	for i, s := range obj.Anames {
    		instructions[s] = obj.As(i)
    	}
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Thu Nov 07 02:20:14 UTC 2024
    - 21.7K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/arm64error.s

    TEXT errors(SB),$0
    	AND	$1, RSP                                          // ERROR "illegal source register"
    	ANDS	$1, R0, RSP                                      // ERROR "illegal combination"
    	ADDSW	R7->32, R14, R13                                 // ERROR "shift amount out of range 0 to 31"
    	ADD	R1.UXTB<<5, R2, R3                               // ERROR "shift amount out of range 0 to 4"
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Mar 26 10:48:50 UTC 2025
    - 37.9K bytes
    - Viewed (0)
  5. api/go1.txt

    pkg debug/macho, type RegsAMD64 struct, R11 uint64
    pkg debug/macho, type RegsAMD64 struct, R12 uint64
    pkg debug/macho, type RegsAMD64 struct, R13 uint64
    pkg debug/macho, type RegsAMD64 struct, R14 uint64
    pkg debug/macho, type RegsAMD64 struct, R15 uint64
    pkg debug/macho, type RegsAMD64 struct, R8 uint64
    pkg debug/macho, type RegsAMD64 struct, R9 uint64
    pkg debug/macho, type RegsAMD64 struct, SI uint64
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Aug 14 18:58:28 UTC 2013
    - 1.7M bytes
    - Viewed (0)
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