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Results 11 - 20 of 25 for filter_height (0.2 sec)
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tensorflow/compiler/mlir/lite/tests/quantize-numeric-verify.mlir
%1 = "tfl.dequantize"(%0) : (tensor<1x5x5x3x!quant.uniform<i8:f32, 0.1>>) -> tensor<1x5x5x3xf32> %2 = "tfl.average_pool_2d"(%1) {filter_height = 5 : i32, filter_width = 5 : i32, fused_activation_function = "NONE", padding = "VALID", stride_h = 5 : i32, stride_w = 5 : i32} : (tensor<1x5x5x3xf32>) -> tensor<1x1x1x3xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 15.1K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/utils/perception_ops_utils.cc
TfLitePoolParams pool_params; llvm::SmallVector<int32_t, 2> pool_size; if (failed(GetIntegerArraySafe(&func_, attrs, "pool_size", &pool_size, 2))) { return failure(); } pool_params.filter_height = pool_size[0]; pool_params.filter_width = pool_size[1]; // Retrieve strides. llvm::SmallVector<int32_t, 2> strides; if (failed(GetIntegerArraySafe(&func_, attrs, "strides", &strides, 2))) {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri May 17 17:58:54 UTC 2024 - 8.9K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/quantize.mlir
%1 = "tfl.max_pool_2d"(%0) {filter_height = 1 : i32, filter_width = 1 : i32, fused_activation_function = "RELU6", padding = "SAME", stride_h = 1 : i32, stride_w = 1 : i32} : (tensor<1x6x6x16xf32>) -> tensor<1x1x1x16xf32> func.return %1 : tensor<1x1x1x16xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue May 28 23:10:13 UTC 2024 - 39.7K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/transforms/optimize_patterns.td
def FuseActivationFuncWithAvgPool#ActFnOp#ActFnAttr : Pat< (ActFnOp (TFL_AveragePool2DOp:$pool_out $input, $filter_height, $filter_width, $padding, $stride_h, $stride_w, TFL_AF_None)), (TFL_AveragePool2DOp $input, $filter_height, $filter_width, $padding, $stride_h, $stride_w, ActFnAttr), [(HasOneUse $pool_out)]>;
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 16 20:31:41 UTC 2024 - 66.4K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/prepare-quantize.mlir
%0 = "tfl.dequantize"(%arg0) : (tensor<1x6x6x16x!quant.uniform<u8:f32, 7.812500e-03:128>>) -> tensor<1x6x6x16xf32> %1 = "tfl.average_pool_2d"(%0) { name = "avgpool", filter_height = 3 : i32, filter_width = 6 : i32, fused_activation_function = "NONE", padding = "VALID", stride_h = 3 : i32, stride_w = 1 : i32 } : (tensor<1x6x6x16xf32>) -> tensor<1x1x1x16xf32> func.return %1 : tensor<1x1x1x16xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 67.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/transforms/prepare_tf.cc
/// format to TFLite DepthwiseConv2D op filter data format and return Value /// for the converted filter. TensorFlow filter data format is /// [filter_height, filter_width, in_channels, channel_multiplier] and TFLite /// filter data format is [1, filter_height, filter_width, out_channels]. /// Requires that filter is verified by the match method that it is a 4-D /// RankedTensorType.
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue May 28 21:49:50 UTC 2024 - 64.6K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/ops.mlir
^bb0(%arg0: tensor<256x32x32x3xf32>): // CHECK: "tfl.max_pool_2d"(%arg0) <{filter_height = 1 : i32, filter_width = 1 : i32, fused_activation_function = "RELU6", padding = "SAME", stride_h = 1 : i32, stride_w = 1 : i32}> : (tensor<256x32x32x3xf32>) -> tensor<?xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Jun 06 19:09:08 UTC 2024 - 189.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/legalize-tf.mlir
%5 = arith.addf %0, %1 : tensor<1x1x1x16xf32> %6 = arith.addf %2, %5 : tensor<1x1x1x16xf32> func.return %6 : tensor<1x1x1x16xf32> // CHECK-LABEL: func @avgPool2D // CHECK: "tfl.average_pool_2d"(%arg0) <{filter_height = 3 : i32, filter_width = 6 : i32, fused_activation_function = "NONE", padding = "VALID", stride_h = 3 : i32, stride_w = 1 : i32}> : (tensor<1x6x6x16xf32>) -> tensor<1x1x1x16xf32> // CHECK: %1 = "tf.AvgPool"(%arg0)
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Jun 05 01:54:33 UTC 2024 - 153.4K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/ir/tf_generated_ops.td
and a filter / kernel tensor of shape `[filter_height, filter_width, in_channels, out_channels]`, this op performs the following: 1. Flattens the filter to a 2-D matrix with shape `[filter_height * filter_width * in_channels, output_channels]`. 2. Extracts image patches from the input tensor to form a *virtual* tensor of shape `[batch, out_height, out_width, filter_height * filter_width * in_channels]`.
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 11 23:24:08 UTC 2024 - 793K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/stablehlo/transforms/legalize_hlo.cc
conv_output_type, rewriter); } Value output; if (is_depthwise_conv && num_spatial_dims == 2) { // Reshapes filter format to [filter_height, filter_width, in_channels, // channel_multiplier] from HLO's [filter_height, filter_width, 1, // in_channels * channel_multiplier] format. auto filter_type = mlir::cast<ShapedType>(rhs.getType());
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Apr 25 16:01:03 UTC 2024 - 154.9K bytes - Viewed (0)