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Results 11 - 17 of 17 for SQRTF (0.12 sec)

  1. src/cmd/compile/internal/ssa/_gen/ARMOps.go

    		{name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"},   // -arg0, float64
    		{name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD"}, // sqrt(arg0), float64
    		{name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF"}, // sqrt(arg0), float32
    		{name: "ABSD", argLength: 1, reg: fp11, asm: "ABSD"},   // abs(arg0), float64
    
    		{name: "CLZ", argLength: 1, reg: gp11, asm: "CLZ"},     // count leading zero
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 24 00:21:13 UTC 2023
    - 41K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/armerror.s

    	NEGF	F0, F1, F2         // ERROR "illegal combination"
    	NEGD	F0, F1, F2         // ERROR "illegal combination"
    	ABSF	F0, F1, F2         // ERROR "illegal combination"
    	ABSD	F0, F1, F2         // ERROR "illegal combination"
    	SQRTF	F0, F1, F2         // ERROR "illegal combination"
    	SQRTD	F0, F1, F2         // ERROR "illegal combination"
    	MOVF	F0, F1, F2         // ERROR "illegal combination"
    	MOVD	F0, F1, F2         // ERROR "illegal combination"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Nov 03 14:06:21 UTC 2017
    - 14.4K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/LOONG64.rules

    // unary ops
    (Neg(64|32|16|8) ...) => (NEGV ...)
    (Neg(32|64)F ...) => (NEG(F|D) ...)
    
    (Com(64|32|16|8) x) => (NOR (MOVVconst [0]) x)
    
    (Sqrt ...) => (SQRTD ...)
    (Sqrt32 ...) => (SQRTF ...)
    
    // boolean ops -- booleans are represented with 0=false, 1=true
    (AndB ...) => (AND ...)
    (OrB ...) => (OR ...)
    (EqB x y) => (XOR (MOVVconst [1]) (XOR <typ.Bool> x y))
    (NeqB ...) => (XOR ...)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 31.8K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/MIPS.rules

    // unary ops
    (Neg(32|16|8) ...) => (NEG ...)
    (Neg(32|64)F ...) => (NEG(F|D) ...)
    
    (Com(32|16|8) x) => (NORconst [0] x)
    
    (Sqrt ...) => (SQRTD ...)
    (Sqrt32 ...) => (SQRTF ...)
    
    // TODO: optimize this case?
    (Ctz32NonZero ...) => (Ctz32 ...)
    
    // count trailing zero
    // 32 - CLZ(x&-x - 1)
    (Ctz32 <t> x) => (SUB (MOVWconst [32]) (CLZ <t> (SUBconst <t> [1] (AND <t> x (NEG <t> x)))))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 35.3K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/MIPS64.rules

    // unary ops
    (Neg(64|32|16|8) ...) => (NEGV ...)
    (Neg(32|64)F ...) => (NEG(F|D) ...)
    
    (Com(64|32|16|8) x) => (NOR (MOVVconst [0]) x)
    
    (Sqrt ...) => (SQRTD ...)
    (Sqrt32 ...) => (SQRTF ...)
    
    // boolean ops -- booleans are represented with 0=false, 1=true
    (AndB ...) => (AND ...)
    (OrB ...) => (OR ...)
    (EqB x y) => (XOR (MOVVconst [1]) (XOR <typ.Bool> x y))
    (NeqB ...) => (XOR ...)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 31 03:59:48 UTC 2023
    - 41.9K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/ARM.rules

    (Xor(32|16|8) ...) => (XOR ...)
    
    // unary ops
    (Neg(32|16|8) x) => (RSBconst [0] x)
    (Neg(32|64)F ...) => (NEG(F|D) ...)
    
    (Com(32|16|8) ...) => (MVN ...)
    
    (Sqrt ...) => (SQRTD ...)
    (Sqrt32 ...) => (SQRTF ...)
    (Abs ...) => (ABSD ...)
    
    // TODO: optimize this for ARMv5 and ARMv6
    (Ctz32NonZero ...) => (Ctz32 ...)
    (Ctz16NonZero ...) => (Ctz32 ...)
    (Ctz8NonZero ...) => (Ctz32 ...)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 90.1K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/opGen.go

    			},
    			outputs: []outputInfo{
    				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
    			},
    		},
    	},
    	{
    		name:   "SQRTF",
    		argLen: 1,
    		asm:    arm.ASQRTF,
    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
    			},
    			outputs: []outputInfo{
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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