narg++

		case xArgRel8:
			inst.PCRelOff = immcpos
			inst.PCRel = 1
			inst.Args[narg] = Rel(int8(immc))
			narg++

		case xArgRel16:
			inst.PCRelOff = immcpos
			inst.PCRel = 2
			inst.Args[narg] = Rel(int16(immc))
			narg++

		case xArgRel32:
			inst.PCRelOff = immcpos
			inst.PCRel = 4
			inst.Args[narg] = Rel(int32(immc))
			narg++
		}
	}

//
// TOC   -> dynamic:              A PLT call stub is generated which saves R2.
//                                 TOC save slot is rewritten to restore TOC.
// NOTOC -> dynamic [P10]:        A stub using pcrel instructions is generated.
// NOTOC -> dynamic [P8/default]: A P8 compatible, non-PIC stub is generated
// NOTOC -> dynamic [P8/pie]:     A P8 compatible, PIC stub is generated
//
//
// Some notes about other cases:

			v := r.addr >> 24
			r.addr &= 0xFFFFFF
			r.type_ = uint8(v & 0xF)
			v >>= 4
			r.length = 1 << (v & 3)
			v >>= 2
			r.pcrel = uint8(v & 1)
			r.value = m.e.Uint32(p[4:])
		} else {
			v := m.e.Uint32(p[4:])
			r.symnum = v & 0xFFFFFF
			v >>= 24
			r.pcrel = uint8(v & 1)
			v >>= 1
			r.length = 1 << (v & 3)
			v >>= 2
			r.extrn = uint8(v & 1)
			v >>= 1
			r.type_ = uint8(v)
		}

(AND <t> x:(MOVDconst [m]) n) && t.Size() == 4 && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(0,m,32)] n)

// When PCRel is supported, paddi can add a 34b signed constant in one instruction.
(ADD (MOVDconst [m]) x) && supportsPPC64PCRel() && (m<<30)>>30 == m => (ADDconst [m] x)

				return fmt.Sprintf(".quad 0x%x", v)
			}
		}
		buf.WriteString(str)

	default:
		// Prefixed load/stores do not print the displacement register when R==1 (they are PCrel).
		// This also implies RA should be 0.  Likewise, when R==0, printing of R can be omitted.
		if strings.HasPrefix(opName, "pl") || strings.HasPrefix(opName, "pst") {
			r := inst.Args[3].(Imm)
			ra := inst.Args[2].(Reg)

			stub.SetUint32(ctxt.Arch, stub.Size()-4, OP_ADDI_R12_R12) // addi  r12,targ@toc@l(r12)

		// A call from PC relative function.
		case STUB_PCREL:
			if buildcfg.GOPPC64 >= 10 {
				// Set up address of targ in r12, PCrel
				stub.AddSymRef(ctxt.Arch, r.Sym(), r.Add(), objabi.R_ADDRPOWER_PCREL34, 8)
				stub.SetUint32(ctxt.Arch, stub.Size()-8, OP_PLA_PFX)
				stub.SetUint32(ctxt.Arch, stub.Size()-4, OP_PLA_SFX_R12) // pla r12, r
			} else {

	if initfunc == nil {
		return
	}

	o := func(op uint32) {
		initfunc.AddUint32(ctxt.Arch, op)
	}

	// Emit the following function:
	//
	//	local.dso_init:
	//		la.pcrel $a0, local.moduledata
	//		b runtime.addmoduledata

	//	0000000000000000 <local.dso_init>:
	//	0:	1a000004	pcalau12i	$a0, 0
	//				0: R_LARCH_PCALA_HI20	local.moduledata
	o(0x1a000004)

		if targType == sym.SDYNIMPORT {
			ldr.Errorf(s, "unexpected R_X86_64_PC32 relocation for dynamic symbol %s", ldr.SymName(targ))
		}
		if targType == 0 || targType == sym.SXREF {
			ldr.Errorf(s, "unknown symbol %s in pcrel", ldr.SymName(targ))
		}
		su := ldr.MakeSymbolUpdater(s)
		su.SetRelocType(rIdx, objabi.R_PCREL)
		su.SetRelocAdd(rIdx, r.Add()+4)
		return true

	case objabi.ElfRelocOffset + objabi.RelocType(elf.R_X86_64_PC64):

		}
	case Imm:
		return fmt.Sprintf("$%d", arg)
	case SpReg:
		switch arg {
		case 8:
			return "LR"
		case 9:
			return "CTR"
		}
		return fmt.Sprintf("SPR(%d)", int(arg))
	case PCRel:
		addr := pc + uint64(int64(arg))
		s, base := symname(addr)
		if s != "" && addr == base {
			return fmt.Sprintf("%s(SB)", s)
		}
		if inst.Op == BL && s != "" && (addr-base) == 8 {

	case arg_slabel_imm14_2:
		imm14 := ((x >> 5) & (1<<14 - 1))
		return PCRel(((int64(imm14) << 2) << 48) >> 48)

	case arg_slabel_imm19_2:
		imm19 := ((x >> 5) & (1<<19 - 1))
		return PCRel(((int64(imm19) << 2) << 43) >> 43)

	case arg_slabel_imm26_2:
		imm26 := (x & (1<<26 - 1))
		return PCRel(((int64(imm26) << 2) << 36) >> 36)

	case arg_slabel_immhi_immlo_0: