FCMPO F1, F2, CR0               // FCMPO F1,CR0,F2 // fc011040
	FCMPU F1, F2                    // fc011000
	FCMPU F1, F2, CR0               // FCMPU F1,CR0,F2 // fc011000
	LVX (R3)(R4), V1                // 7c2418ce
	LVX (R3)(R0), V1                // 7c2018ce
	LVX (R3), V1                    // 7c2018ce
	LVXL (R3)(R4), V1               // 7c241ace
	LVXL (R3)(R0), V1               // 7c201ace
	LVXL (R3), V1                   // 7c201ace

// VSUBUQM, VSUBCUQ, and VSEL instructions.

// 2. ppc64 does not have a multiply high and low
// like s390x, so those were implemented using
// macros to compute the equivalent values.

// 3. The LVX, STVX instructions on ppc64 require
// 16 byte alignment of the data.  To avoid that
// requirement, data is loaded using LXVD2X and
// STXVD2X with VPERM to reorder bytes correctly.

	MOVD    in+32(FP), BLK_INP
	MOVD    in_len+40(FP), IN_LEN
	MOVD    counter+56(FP), COUNTER
	MOVD    key+64(FP), BLK_KEY

// Set up permute string when needed.
#ifdef NEEDS_ESPERM
	MOVD    $·rcon(SB), R14
	LVX     (R14), ESPERM   // Permute value for P8_ macros.
#endif
	SETUP_COUNTER		// V30 Counter V31 BE {0, 0, 0, 1}
	LOAD_KEYS(BLK_KEY, KEY_LEN)	// VS1 - VS10/12/14 based on keysize
	CMP     IN_LEN, $128
	BLT	block64

	STWCIX:         "stwcix",
	ISEL:           "isel",
	LVEBX:          "lvebx",
	LVEHX:          "lvehx",
	LVEWX:          "lvewx",
	LVSL:           "lvsl",
	LVSR:           "lvsr",
	LVX:            "lvx",
	LVXL:           "lvxl",
	MFVSCR:         "mfvscr",
	MTVSCR:         "mtvscr",
	STVEBX:         "stvebx",
	STVEHX:         "stvehx",
	STVEWX:         "stvewx",
	STVX:           "stvx",

			opset(AMOVHU, r0)

			opset(AMOVHZU, r0)
			opset(AMOVWU, r0)
			opset(AMOVWZU, r0)
			opset(AMOVDU, r0)
			opset(AMOVMW, r0)

		case ALVEBX: /* lvebx, lvehx, lvewx, lvx, lvxl, lvsl, lvsr */
			opset(ALVEHX, r0)
			opset(ALVEWX, r0)
			opset(ALVX, r0)
			opset(ALVXL, r0)
			opset(ALVSL, r0)
			opset(ALVSR, r0)