FMSUBS F1, F2, F3, F4           // ec8110f8
	FMSUBSCC F1, F2, F3, F4         // ec8110f9
	FNMADD F1, F2, F3, F4           // fc8110fe
	FNMADDCC F1, F2, F3, F4         // fc8110ff
	FNMADDS F1, F2, F3, F4          // ec8110fe
	FNMADDSCC F1, F2, F3, F4        // ec8110ff
	FNMSUB F1, F2, F3, F4           // fc8110fc
	FNMSUBCC F1, F2, F3, F4         // fc8110fd
	FNMSUBS F1, F2, F3, F4          // ec8110fc

}
func rewriteValueRISCV64_OpRISCV64FMSUBS(v *Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (FMSUBS neg:(FNEGS x) y z)
	// cond: neg.Uses == 1
	// result: (FNMADDS x y z)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			neg := v_0
			if neg.Op != OpRISCV64FNEGS {
				continue
			}
			x := neg.Args[0]
			y := v_1
			z := v_2

	FMADDS	F1, F3, F2, F4                  // 440c011f
	FMADDD	F4, F5, F4, F4                  // 8414441f
	FMSUBS	F13, F21, F13, F19              // b3d50d1f
	FMSUBD	F11, F7, F15, F31               // ff9d4b1f
	FNMADDS	F1, F3, F2, F4                  // 440c211f
	FNMADDD	F1, F3, F2, F4                  // 440c611f
	FNMSUBS	F1, F3, F2, F4                  // 448c211f
	FNMSUBD	F1, F3, F2, F4                  // 448c611f

(FSUBS a (FNMULS x y)) && a.Block.Func.useFMA(v) => (FMADDS  a x y)
(FSUBD a (FNMULD x y)) && a.Block.Func.useFMA(v) => (FMADDD  a x y)
(FSUBS (FNMULS x y) a) && a.Block.Func.useFMA(v) => (FNMADDS a x y)
(FSUBD (FNMULD x y) a) && a.Block.Func.useFMA(v) => (FNMADDD a x y)

(MOVBUload [off] {sym} (SB) _) && symIsRO(sym) => (MOVDconst [int64(read8(sym, int64(off)))])

		if !(a.Block.Func.useFMA(v)) {
			break
		}
		v.reset(OpARM64FMADDS)
		v.AddArg3(a, x, y)
		return true
	}
	// match: (FSUBS (FNMULS x y) a)
	// cond: a.Block.Func.useFMA(v)
	// result: (FNMADDS a x y)
	for {
		if v_0.Op != OpARM64FNMULS {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		a := v_1
		if !(a.Block.Func.useFMA(v)) {
			break
		}
		v.reset(OpARM64FNMADDS)

				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "FNMADDS",
		argLen: 3,
		asm:    arm64.AFNMADDS,
		reg: regInfo{
			inputs: []inputInfo{