d = divd / divr
		// amd64:-"JMP"
		// 386:-"JMP"
		e = divd % divr
		d += e
	}
	return d, e
}

// Check that len() and cap() calls divided by powers of two are
// optimized into shifts and ands

func LenDiv1(a []int) int {
	// 386:"SHRL\t[$]10"
	// amd64:"SHRQ\t[$]10"
	// arm64:"LSR\t[$]10",-"SDIV"
	// arm:"SRL\t[$]10",-".*udiv"
	// ppc64x:"SRD"\t[$]10"
	return len(a) / 1024
}

{"Name":"ANDS (immediate)","Bits":"0|1|1|1|0|0|1|0|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"ANDS <Wd>, <Wn>, #<imm>","Code":"","Alias":"This instruction is used by the alias TST (immediate)."},

    assertEqualHashCode(Predicates.and(p1, p2), Predicates.and(p1, p2));

    assertEqualHashCode(Predicates.or(p1, p2), Predicates.or(p1, p2));

    // While not a contractual requirement, we'd like the hash codes for ands
    // & ors of the same predicates to not collide.
    assertTrue(Predicates.and(p1, p2).hashCode() != Predicates.or(p1, p2).hashCode());
  }

  @J2ktIncompatible
  @GwtIncompatible // reflection

    assertEqualHashCode(Predicates.and(p1, p2), Predicates.and(p1, p2));

    assertEqualHashCode(Predicates.or(p1, p2), Predicates.or(p1, p2));

    // While not a contractual requirement, we'd like the hash codes for ands
    // & ors of the same predicates to not collide.
    assertTrue(Predicates.and(p1, p2).hashCode() != Predicates.or(p1, p2).hashCode());
  }

  @J2ktIncompatible
  @GwtIncompatible // reflection

	var op int16
	switch p.next().ScanToken {
	case lex.LSH:
		op = 0
	case lex.RSH:
		op = 1
	case lex.ARR:
		op = 2
	case lex.ROT:
		// following instructions on ARM64 support rotate right
		// AND, ANDS, TST, BIC, BICS, EON, EOR, ORR, MVN, ORN
		op = 3
	}
	tok := p.next()
	str := tok.String()
	var count int16
	switch tok.ScanToken {
	case scanner.Ident:
		if p.arch.Family == sys.ARM64 {

(MOVHUreg <t> x:(MOVHload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVHUload <t> [off] {sym} ptr mem)

// fold extensions and ANDs together
(MOVBUreg (ANDconst [c] x)) => (ANDconst [c&0xff] x)
(MOVHUreg (ANDconst [c] x)) => (ANDconst [c&0xffff] x)
(MOVBreg (ANDconst [c] x)) && c & 0x80   == 0 => (ANDconst [c&0x7f] x)

(ANDQ (MOVQconst [c]) x) && isUint64PowerOfTwo(^c) && uint64(^c) >= 1<<31 => (BTRQconst [int8(log64(^c))] x)

// Special-case bit patterns on first/last bit.
// generic.rules changes ANDs of high-part/low-part masks into a couple of shifts,
// for instance:
//    x & 0xFFFF0000 -> (x >> 16) << 16
//    x & 0x80000000 -> (x >> 31) << 31
//

(MOVHreg x:(MOVBUload _ _)) => (MOVWreg x)
(MOVHreg x:(MOVHload _ _)) => (MOVWreg x)
(MOVHUreg x:(MOVBUload _ _)) => (MOVWreg x)
(MOVHUreg x:(MOVHUload _ _)) => (MOVWreg x)

// fold extensions and ANDs together
(MOVBUreg (ANDconst [c] x)) => (ANDconst [c&0xff] x)
(MOVHUreg (ANDconst [c] x)) => (ANDconst [c&0xffff] x)
(MOVBreg (ANDconst [c] x)) && c & 0x80 == 0 => (ANDconst [c&0x7f] x)

(Less16 (Const16 <t> [math.MaxInt16-1]) x) => (Eq16 x (Const16 <t> [math.MaxInt16]))
(Less8  (Const8  <t> [math.MaxInt8 -1]) x) => (Eq8  x (Const8  <t> [math.MaxInt8 ]))

// Ands clear bits. Ors set bits.
// If a subsequent Or will set all the bits
// that an And cleared, we can skip the And.
// This happens in bitmasking code like:
//   x &^= 3 << shift // clear two old bits