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Results 11 - 20 of 58 for MOVW (0.08 sec)

  1. src/internal/runtime/atomic/atomic_arm.s

    TEXT armCas64<>(SB),NOSPLIT,$0-21
    	// addr is already in R1
    	MOVW	old_lo+4(FP), R2
    	MOVW	old_hi+8(FP), R3
    	MOVW	new_lo+12(FP), R4
    	MOVW	new_hi+16(FP), R5
    cas64loop:
    	LDREXD	(R1), R6	// loads R6 and R7
    	CMP	R2, R6
    	BNE	cas64fail
    	CMP	R3, R7
    	BNE	cas64fail
    
    	DMB	MB_ISHST
    
    	STREXD	R4, (R1), R0	// stores R4 and R5
    	CMP	$0, R0
    	BNE	cas64loop
    	MOVW	$1, R0
    
    	DMB	MB_ISH
    
    	MOVBU	R0, swapped+20(FP)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 25 19:53:03 UTC 2024
    - 5.7K bytes
    - Viewed (0)
  2. src/internal/runtime/atomic/sys_linux_arm.s

    TEXT memory_barrier<>(SB),NOSPLIT|NOFRAME,$0
    	MOVW	$0xffff0fa0, R15 // R15 is hardware PC.
    
    TEXT	·Load(SB),NOSPLIT,$0-8
    	MOVW	addr+0(FP), R0
    	MOVW	(R0), R1
    
    	MOVB	runtime·goarm(SB), R11
    	CMP	$7, R11
    	BGE	native_barrier
    	BL	memory_barrier<>(SB)
    	B	end
    native_barrier:
    	DMB	MB_ISH
    end:
    	MOVW	R1, ret+4(FP)
    	RET
    
    TEXT	·Store(SB),NOSPLIT,$0-8
    	MOVW	addr+0(FP), R1
    	MOVW	v+4(FP), R2
    
    	MOVB	runtime·goarm(SB), R8
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 25 19:53:03 UTC 2024
    - 2.8K bytes
    - Viewed (0)
  3. src/crypto/md5/md5block_arm64.s

    	LDPW	(1*8)(R0), (R6, R7)
    
    loop:
    	MOVW	R4, R12
    	MOVW	R5, R13
    	MOVW	R6, R14
    	MOVW	R7, R15
    
    	MOVW	(0*4)(R1), R8
    	MOVW	R7, R9
    
    #define ROUND1(a, b, c, d, index, const, shift) \
    	ADDW	$const, a; \
    	ADDW	R8, a; \
    	MOVW	(index*4)(R1), R8; \
    	EORW	c, R9; \
    	ANDW	b, R9; \
    	EORW	d, R9; \
    	ADDW	R9, a; \
    	RORW	$(32-shift), a; \
    	MOVW	c, R9; \
    	ADDW	b, a
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 4.1K bytes
    - Viewed (0)
  4. src/internal/runtime/atomic/atomic_arm64.s

    TEXT ·Xchg(SB), NOSPLIT, $0-20
    	MOVD	ptr+0(FP), R0
    	MOVW	new+8(FP), R1
    #ifndef GOARM64_LSE
    	MOVBU	internal∕cpu·ARM64+const_offsetARM64HasATOMICS(SB), R4
    	CBZ 	R4, load_store_loop
    #endif
    	SWPALW	R1, (R0), R2
    	MOVW	R2, ret+16(FP)
    	RET
    #ifndef GOARM64_LSE
    load_store_loop:
    	LDAXRW	(R0), R2
    	STLXRW	R1, (R0), R3
    	CBNZ	R3, load_store_loop
    	MOVW	R2, ret+16(FP)
    	RET
    #endif
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 25 19:53:03 UTC 2024
    - 9K bytes
    - Viewed (0)
  5. src/crypto/md5/md5block_arm.s

    	MOVW	$buf, Rtable	// to
    	MOVW	$64, Rc0		// n
    	MOVM.IB	[Rtable,Rdata,Rc0], (R13)
    	BL	runtime·memmove(SB)
    
    	// Point to the local aligned copy of the data
    	MOVW	$buf, Rdata
    
    aligned:
    	// Point to the table of constants
    	// A PC relative add would be cheaper than this
    	MOVW	$·table(SB), Rtable
    
    	// Load up initial MD5 accumulator
    	MOVW	dig+0(FP), Rc0
    	MOVM.IA (Rc0), [Ra,Rb,Rc,Rd]
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 8.8K bytes
    - Viewed (0)
  6. src/cmd/asm/internal/asm/testdata/loong64enc1.s

    	BNE	R0, R4, 1(PC)		// 80040044
    	BLTU	R4, 1(PC)		// 80040068
    	MOVW	y+8(FP), F4		// 6440002b
    	MOVF	y+8(FP), F4		// 6440002b
    	MOVD	y+8(FP), F4		// 6440802b
    	MOVW	1(F5), F4		// a404002b
    	MOVF	1(F5), F4		// a404002b
    	MOVD	1(F5), F4		// a404802b
    	MOVW	F4, result+16(FP)	// 6460402b
    	MOVF	F4, result+16(FP)	// 6460402b
    	MOVD	F4, result+16(FP)	// 6460c02b
    	MOVW	F4, 1(F5)		// a404402b
    	MOVF	F4, 1(F5)		// a404402b
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 8.2K bytes
    - Viewed (0)
  7. src/internal/runtime/atomic/sys_nonlinux_arm.s

    TEXT	·Load(SB),NOSPLIT|NOFRAME,$0-8
    	MOVW	addr+0(FP), R0
    	MOVW	(R0), R1
    
    	MOVB	runtime·goarm(SB), R11
    	CMP	$7, R11
    	BLT	2(PC)
    	DMB	MB_ISH
    
    	MOVW	R1, ret+4(FP)
    	RET
    
    TEXT	·Store(SB),NOSPLIT,$0-8
    	MOVW	addr+0(FP), R1
    	MOVW	v+4(FP), R2
    
    	MOVB	runtime·goarm(SB), R8
    	CMP	$7, R8
    	BLT	2(PC)
    	DMB	MB_ISH
    
    	MOVW	R2, (R1)
    
    	CMP	$7, R8
    	BLT	2(PC)
    	DMB	MB_ISH
    	RET
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 25 19:53:03 UTC 2024
    - 1.3K bytes
    - Viewed (0)
  8. src/internal/runtime/atomic/atomic_loong64.s

    TEXT ·Or32(SB), NOSPLIT, $0-20
    	MOVV	ptr+0(FP), R4
    	MOVW	val+8(FP), R5
    	DBAR
    	LL	(R4), R6
    	OR	R5, R6, R7
    	SC	R7, (R4)
    	BEQ	R7, -4(PC)
    	DBAR
    	MOVW R6, ret+16(FP)
    	RET
    
    // func And32(addr *uint32, v uint32) old uint32
    TEXT ·And32(SB), NOSPLIT, $0-20
    	MOVV	ptr+0(FP), R4
    	MOVW	val+8(FP), R5
    	DBAR
    	LL	(R4), R6
    	AND	R5, R6, R7
    	SC	R7, (R4)
    	BEQ	R7, -4(PC)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 25 19:53:03 UTC 2024
    - 6.3K bytes
    - Viewed (0)
  9. src/internal/runtime/atomic/atomic_s390x.s

    TEXT ·Or32(SB), NOSPLIT, $0-20
    	MOVD	ptr+0(FP), R4
    	MOVW	val+8(FP), R5
    	MOVW	(R4), R3
    repeat:
    	OR	R5, R3, R6
    	CS	R3, R6, (R4) // if R3==(R4) then (R4)=R6 else R3=(R4)
    	BNE	repeat
    	MOVW	R3, ret+16(FP)
    	RET
    
    // func And32(addr *uint32, v uint32) old uint32
    TEXT ·And32(SB), NOSPLIT, $0-20
    	MOVD	ptr+0(FP), R4
    	MOVW	val+8(FP), R5
    	MOVW	(R4), R3
    repeat:
    	AND	R5, R3, R6
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 25 19:53:03 UTC 2024
    - 7.1K bytes
    - Viewed (0)
  10. src/internal/runtime/atomic/atomic_mips64x.s

    TEXT ·Or32(SB), NOSPLIT, $0-20
    	MOVV	ptr+0(FP), R1
    	MOVW	val+8(FP), R2
    
    	SYNC
    	LL	(R1), R3
    	OR	R2, R3, R4
    	SC	R4, (R1)
    	BEQ	R4, -3(PC)
    	SYNC
    	MOVW	R3, ret+16(FP)
    	RET
    
    // func And32(addr *uint32, v uint32) old uint32
    TEXT ·And32(SB), NOSPLIT, $0-20
    	MOVV	ptr+0(FP), R1
    	MOVW	val+8(FP), R2
    
    	SYNC
    	LL	(R1), R3
    	AND	R2, R3, R4
    	SC	R4, (R1)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sat May 11 21:29:34 UTC 2024
    - 7.2K bytes
    - Viewed (0)
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