- Sort Score
- Result 10 results
- Languages All
Results 11 - 16 of 16 for ADDL (0.06 sec)
-
src/crypto/aes/gcm_amd64.s
#define ctx DX #define ctrPtr CX #define ptx SI #define ks AX #define tPtr R8 #define ptxLen R9 #define aluCTR R10 #define aluTMP R11 #define aluK R12 #define NR R13 #define increment(i) ADDL $1, aluCTR; MOVL aluCTR, aluTMP; XORL aluK, aluTMP; BSWAPL aluTMP; MOVL aluTMP, (3*4 + 8*16 + i*16)(SP) #define aesRnd(k) AESENC k, B0; AESENC k, B1; AESENC k, B2; AESENC k, B3; AESENC k, B4; AESENC k, B5; AESENC k, B6; AESENC k, B7
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 23.4K bytes - Viewed (0) -
src/runtime/race_amd64.s
// Add TEXT sync∕atomic·AddInt32(SB), NOSPLIT|NOFRAME, $0-20 GO_ARGS MOVQ $__tsan_go_atomic32_fetch_add(SB), AX CALL racecallatomic<>(SB) MOVL add+8(FP), AX // convert fetch_add to add_fetch ADDL AX, ret+16(FP) RET TEXT sync∕atomic·AddInt64(SB), NOSPLIT|NOFRAME, $0-24 GO_ARGS MOVQ $__tsan_go_atomic64_fetch_add(SB), AX CALL racecallatomic<>(SB) MOVQ add+8(FP), AX // convert fetch_add to add_fetch
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 18:37:29 UTC 2024 - 15.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64.rules
// Atomic adds. (AtomicAdd32 ptr val mem) => (AddTupleFirst32 val (XADDLlock val ptr mem)) (AtomicAdd64 ptr val mem) => (AddTupleFirst64 val (XADDQlock val ptr mem)) (Select0 <t> (AddTupleFirst32 val tuple)) => (ADDL val (Select0 <t> tuple)) (Select1 (AddTupleFirst32 _ tuple)) => (Select1 tuple) (Select0 <t> (AddTupleFirst64 val tuple)) => (ADDQ val (Select0 <t> tuple)) (Select1 (AddTupleFirst64 _ tuple)) => (Select1 tuple)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteAMD64.go
// result: (LEAL2 x y) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { x := v_0 if v_1.Op != OpAMD64SHLLconst || auxIntToInt8(v_1.AuxInt) != 1 { continue } y := v_1.Args[0] v.reset(OpAMD64LEAL2) v.AddArg2(x, y) return true } break } // match: (ADDL x (ADDL y y)) // result: (LEAL2 x y) for {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 712.7K bytes - Viewed (0) -
src/cmd/internal/obj/x86/asm6.go
// {Yi32, Ynone, Yax, Zil_, 1}, // {Yi32, Ynone, Yml, Zilo_m, 2}, // {Yrl, Ynone, Yml, Zr_m, 1}, // {Yml, Ynone, Yrl, Zm_r, 1}, // } // // so there are 5 possible types of ADDL instruction that can be laid down, and // possible states used to lay them down (Ztype and z pointer, assuming z // points at opBytes{0x83, 00, 0x05,0x81, 00, 0x01, 0x03}) are: // // Yi8, Yml -> Zibo_m, z (0x83, 00)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 146.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
{1, 65791}, // AX CX DX BX SP BP SI DI SB }, outputs: []outputInfo{ {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 }, }, }, { name: "ADDL", argLen: 2, commutative: true, clobberFlags: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 239}, // AX CX DX BX BP SI DI
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)