}

// merge ubfx and zero-extension into ubfx.
func ubfx15(x uint64) bool {
	midr := x + 10
	part_num := uint16((midr >> 4) & 0xfff)
	if part_num == 0xd0c { // arm64:"UBFX\t[$]4, R[0-9]+, [$]12",-"MOVHU\tR[0-9]+, R[0-9]+"
		return true
	}
	return false
}

// merge ANDconst and ubfx into ubfx
func ubfx16(x uint64) uint64 {
	// arm64:"UBFX\t[$]4, R[0-9]+, [$]6",-"AND\t[$]63"

	MOVBU (R2)(R8.SXTX), R19                   // 53e86838
	MOVBU (R27)(R23), R14                      // 6e6b7738
	MOVHU.P 107(R14), R13                      // cdb54678
	MOVHU.W 192(R3), R2                        // 620c4c78
	MOVHU 6844(R4), R19                        // 93787579
	MOVHU (R5)(R25.SXTW), R15                  // afc87978
	//TODO MOVBW.P 77(R19), R11                // 6bd6c438

	// wasm:"I64Ctz"
	return bits.TrailingZeros32(n)
}

func TrailingZeros16(n uint16) int {
	// amd64:"BSFL","ORL\\t\\$65536"
	// 386:"BSFL\t"
	// arm:"ORR\t\\$65536","CLZ",-"MOVHU\tR"
	// arm64:"ORR\t\\$65536","RBITW","CLZW",-"MOVHU\tR",-"RBIT\t",-"CLZ\t"
	// s390x:"FLOGR","OR\t\\$65536"
	// ppc64x/power8:"POPCNTD","ORIS\\t\\$1"
	// ppc64x/power9:"CNTTZD","ORIS\\t\\$1"
	// wasm:"I64Ctz"
	return bits.TrailingZeros16(n)

		{name: "MOVHUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVHU", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux.  arg1=mem.

	SD	X6, 4096(X5)

	FLW	4096(X5), F6
	FLD	4096(X5), F6
	FSW	F6, 4096(X5)
	FSD	F6, 4096(X5)

	MOVB	4096(X5), X6
	MOVH	4096(X5), X6
	MOVW	4096(X5), X6
	MOV	4096(X5), X6
	MOVBU	4096(X5), X6
	MOVHU	4096(X5), X6
	MOVWU	4096(X5), X6

	MOVB	X6, 4096(X5)
	MOVH	X6, 4096(X5)
	MOVW	X6, 4096(X5)
	MOV	X6, 4096(X5)

	MOVF	4096(X5), F6
	MOVD	4096(X5), F6
	MOVF	F6, 4096(X5)
	MOVD	F6, 4096(X5)

	var src, dst, kind asmKind
	op := m[1]
	switch fn.arch.name + "." + op {
	case "386.FMOVLP":
		src, dst = 8, 4
	case "arm.MOVD":
		src = 8
	case "arm.MOVW":
		src = 4
	case "arm.MOVH", "arm.MOVHU":
		src = 2
	case "arm.MOVB", "arm.MOVBU":
		src = 1
	// LEA* opcodes don't really read the second arg.
	// They just take the address of it.
	case "386.LEAL":
		dst = 4
		addr = true

		}

		/* ArmV4 ops: */
	case 70: /* movh/movhu R,O(R) -> strh */
		c.aclass(&p.To)

		r := int(p.To.Reg)
		if r == 0 {
			r = int(o.param)
		}
		o1 = c.oshr(int(p.From.Reg), int32(c.instoffset), r, int(p.Scond))

	case 71: /* movb/movh/movhu O(R),R -> ldrsb/ldrsh/ldrh */
		c.aclass(&p.From)

		r := int(p.From.Reg)
		if r == 0 {

		{name: "MOVHUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVHU", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux.  arg1=mem.

		{name: "MOVHUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVHU", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux.  arg1=mem.

	case LDRB_EQ, UXTB_EQ:
		op = "MOVBU" + op[4:] + suffix
	case LDRSB_EQ:
		op = "MOVBS" + op[5:] + suffix
	case SXTB_EQ:
		op = "MOVBS" + op[4:] + suffix
	case LDRH_EQ, UXTH_EQ:
		op = "MOVHU" + op[4:] + suffix
	case LDRSH_EQ:
		op = "MOVHS" + op[5:] + suffix
	case SXTH_EQ:
		op = "MOVHS" + op[4:] + suffix
	case STR_EQ:
		op = "MOVW" + op[3:] + suffix
		args[0], args[1] = args[1], args[0]