bool IsDynamicPadderOp(const TypeID& type_id);

// Returns True if this op has a Tf2XLA fallback. Currently, this is not the
// inverse of the !IsOpLegalizedWithMlir, but it should be.
bool HasTf2XlaFallback(const TypeID& type_id);

// Whether this type is allowed to have a TF2XLA fallback.
bool IsOpAllowedTf2xlaFallback(const TypeID& type_id);

// Whether this type is Preferred to use a TF2XLA fallback kernel when using

      TypeID::get<TF::CosOp>(),
      TypeID::get<TF::TanOp>(),
      TypeID::get<TF::DiagPartOp>(),
      TypeID::get<TF::EinsumOp>(),
      TypeID::get<TF::ExpOp>(),
      TypeID::get<TF::Expm1Op>(),
      TypeID::get<TF::FakeQuantWithMinMaxArgsOp>(),
      TypeID::get<TF::FloorOp>(),
      TypeID::get<TF::IFFTOp>(),
      TypeID::get<TF::ImagOp>(),
      TypeID::get<TF::IsFiniteOp>(),
      TypeID::get<TF::IsInfOp>(),

  std::string description;
  mlir::TypeID type_id;
  std::unique_ptr<TargetHardware> target_hardware;
  std::function<std::unique_ptr<TargetHardware>()> target_hardware_factory;
};

struct RegisteredTargetHardwareOps {
  explicit RegisteredTargetHardwareOps(mlir::TypeID hardware_type)
      : hardware_typeid(hardware_type) {}
  // Key is the Operation TypeID
  llvm::DenseMap<mlir::TypeID, std::unique_ptr<TargetHardwareOperation>>

    // TODO(b/177376459): remove this.
    internal::RegisterTargetHardwareOp(mlir::TypeID::get<Hardware>(),
                                       mlir::TypeID::get<Op>(),
                                       target_hardware_op_factory);
    internal::RegisterTargetHardwareOpFactory(mlir::TypeID::get<Hardware>(),
                                              mlir::TypeID::get<Op>(),
                                              target_hardware_op_factory);

	case 3: /* mov $soreg/16con, r ==> addi/ori $i,reg',r */
		d := c.vregoff(&p.From)

		v := int32(d)
		r := int(p.From.Reg)

		if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 && (r != 0 || v != 0) {
			c.ctxt.Diag("literal operation on R0\n%v", p)
		}
		if int64(int16(d)) == d {
			// MOVD $int16, Ry  or  MOVD $offset(Rx), Ry

        TypeID type_id = effect.getResource()->getResourceID();
        ResourceId resource_id = GetOpResourceId(type_id, instance_str.value());
        side_effects.SetResourceId(resource_id);
        UpdateSideEffectsByResourceId(side_effects,
                                      side_effects_by_resource_id);
        if (ResourceEffects::IsOnlySelfDependent(type_id)) {

    }

    val result =
      reader.read(name) {
        codec.decode(reader)
      }

    if (typeHint) {
      reader.typeHint = result
    }

    return result
  }

  override fun toDer(
    writer: DerWriter,
    value: T,
  ) {
    if (typeHint) {
      writer.typeHint = value
    }

    if (isOptional && value == defaultValue) {
      // Nothing to write!
      return
    }

			rest = after
		} else {
			return nil, data
		}

		var typeLine []byte
		typeLine, rest = getLine(rest)
		if !bytes.HasSuffix(typeLine, pemEndOfLine) {
			continue
		}
		typeLine = typeLine[0 : len(typeLine)-len(pemEndOfLine)]

		p = &Block{
			Headers: make(map[string]string),
			Type:    string(typeLine),
		}

		for {
			// This loop terminates because getLine's second result is

  static auto* ops = [] {
    llvm::SmallDenseSet<mlir::TypeID, 32>* ops_set =
        new llvm::SmallDenseSet<mlir::TypeID, 32>{
            TypeID::get<mlir::ModuleOp>(),
            TypeID::get<mlir::tf_executor::GraphOp>(),
            TypeID::get<mlir::func::ReturnOp>(),
            TypeID::get<mlir::func::FuncOp>(),
            TypeID::get<mlir::tf_executor::YieldOp>(),
            TypeID::get<mlir::tf_executor::IslandOp>(),

}

// int returns the signed int at the input point, as an int (not int64).
func (deb *debugger) int() int {
	return int(deb.int64())
}

// typeId returns the type id at the input point.
func (deb *debugger) typeId() typeId {
	return typeId(deb.int64())
}

// string returns the string at the input point.
func (deb *debugger) string() string {
	x := int(deb.uint64())
	b := make([]byte, x)