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Results 11 - 20 of 142 for r13 (0.3 sec)
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src/runtime/asm_arm.s
MOVW R4, 12(R13) MOVW R5, 16(R13) MOVW R6, 20(R13) MOVW R7, 24(R13) MOVW R8, 28(R13) MOVW g, 32(R13) MOVW R11, 36(R13) // Skip floating point registers on goarmsoftfp != 0. MOVB runtime·goarmsoftfp(SB), R11 CMP $0, R11 BNE skipfpsave MOVD F8, (40+8*0)(R13) MOVD F9, (40+8*1)(R13) MOVD F10, (40+8*2)(R13) MOVD F11, (40+8*3)(R13) MOVD F12, (40+8*4)(R13)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 23 21:00:52 UTC 2024 - 32.1K bytes - Viewed (0) -
src/runtime/sys_netbsd_arm.s
MOVW $2, R4 // arg 5 - vers MOVW R4, 4(R13) ADD $4, R13 // pass arg 5 on stack SWI $SYS___sigaction_sigtramp SUB $4, R13 MOVW.CS $3, R8 // crash on syscall failure MOVW.CS R8, (R8) RET TEXT runtime·sigfwd(SB),NOSPLIT,$0-16 MOVW sig+4(FP), R0 MOVW info+8(FP), R1 MOVW ctx+12(FP), R2 MOVW fn+0(FP), R11 MOVW R13, R4 SUB $24, R13 BIC $0x7, R13 // alignment for ELF ABI BL (R11)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Jun 06 18:49:01 UTC 2023 - 10.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, { name: "CMPW", argLen: 2, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 }, }, }, {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
// { // outcode(int($1), &$2, 0, &$4); // } SUB R14, R13 // 01ae6822 SUBU R14, R13 // 01ae6823 SUBV R4, R3 // 0064182e SUBVU R4, R3 // 0064182f // LSUBW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } SUB $6512, R13 // 21ade690 SUB $-6512, R13 // 21ad1970 SUBU $6512, R13 // 25ade690 SUBV $9531, R16 // 6210dac5 SUBV $-9531, R13 // 61ad253b SUBVU $9531, R16 // 6610dac5
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0) -
src/runtime/sys_linux_arm.s
CMP $0, R0 BEQ 3(PC) MOVW R0, ret+20(FP) RET // Paranoia: check that SP is as we expect. Use R13 to avoid linker 'fixup' NOP R13 // tell vet SP/R13 changed - stop checking offsets MOVW 12(R13), R0 MOVW $1234, R1 CMP R0, R1 BEQ 2(PC) BL runtime·abort(SB) MOVW 0(R13), R8 // m MOVW 4(R13), R0 // g CMP $0, R8 BEQ nog CMP $0, R0 BEQ nog MOVW R0, g
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 24 18:53:44 UTC 2023 - 13.5K bytes - Viewed (0) -
src/runtime/memmove_arm64.s
LDP -16(R4), (R6, R7) STP (R12, R13), -16(R5) LDP -32(R4), (R8, R9) LDP -48(R4), (R10, R11) LDP.W -64(R4), (R12, R13) SUB R14, R5, R5 SUBS $128, R2, R2 BLS copy64_from_start loop64_backward: STP (R6, R7), -16(R5) LDP -16(R4), (R6, R7) STP (R8, R9), -32(R5) LDP -32(R4), (R8, R9) STP (R10, R11), -48(R5) LDP -48(R4), (R10, R11) STP.W (R12, R13), -64(R5) LDP.W -64(R4), (R12, R13)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 18 18:26:13 UTC 2022 - 6K bytes - Viewed (0) -
src/cmd/dist/vfp_arm.s
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 651 bytes - Viewed (0) -
src/crypto/sha256/sha256block_amd64.s
SHA256ROUND0(5, 0x59f111f1, R11, R12, R13, R14, R15, R8, R9, R10) SHA256ROUND0(6, 0x923f82a4, R10, R11, R12, R13, R14, R15, R8, R9) SHA256ROUND0(7, 0xab1c5ed5, R9, R10, R11, R12, R13, R14, R15, R8) SHA256ROUND0(8, 0xd807aa98, R8, R9, R10, R11, R12, R13, R14, R15) SHA256ROUND0(9, 0x12835b01, R15, R8, R9, R10, R11, R12, R13, R14) SHA256ROUND0(10, 0x243185be, R14, R15, R8, R9, R10, R11, R12, R13)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 47.3K bytes - Viewed (0) -
src/crypto/subtle/xor_arm64.s
less_than32: TBZ $4, R3, less_than16 LDP.P 16(R1), (R11, R12) LDP.P 16(R2), (R13, R14) EOR R11, R13, R13 EOR R12, R14, R14 STP.P (R13, R14), 16(R0) less_than16: TBZ $3, R3, less_than8 MOVD.P 8(R1), R11 MOVD.P 8(R2), R12 EOR R11, R12, R12 MOVD.P R12, 8(R0) less_than8: TBZ $2, R3, less_than4 MOVWU.P 4(R1), R13 MOVWU.P 4(R2), R14 EORW R13, R14, R14 MOVWU.P R14, 4(R0) less_than4: TBZ $1, R3, less_than2
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Aug 17 18:47:33 UTC 2022 - 1.5K bytes - Viewed (0) -
src/math/big/arith_arm64.s
ORR R7, R9 LSL R3, R6, R8 SUB $2, R1 STP.W (R9, R10), -16(R0) loop: CBZ R1, done LDP.W -32(R2), (R10, R11) LDP 16(R2), (R12, R13) LSR R4, R13, R23 ORR R8, R23 // z[i] = (x[i] << s) | (x[i-1] >> (64 - s)) LSL R3, R13 LSR R4, R12, R22 ORR R13, R22 LSL R3, R12 LSR R4, R11, R21 ORR R12, R21 LSL R3, R11 LSR R4, R10, R20 ORR R11, R20 LSL R3, R10, R8
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 11.8K bytes - Viewed (0)