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Results 11 - 20 of 25 for SIMD (0.04 sec)
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src/vendor/golang.org/x/crypto/internal/poly1305/sum_s390x.s
// powers of r that we need from the original equation. // // Notation: // // h - accumulator // r - key // m - message // // [a, b] - SIMD register holding two 64-bit values // [a, b, c, d] - SIMD register holding four 32-bit values // xᵢ[n] - limb n of variable x with bit width i // // Limbs are expressed in little endian order, so for 26-bit
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 17.5K bytes - Viewed (0) -
src/internal/cpu/cpu.go
HasSHA2 bool HasSHA512 bool HasCRC32 bool HasATOMICS bool HasCPUID bool IsNeoverse bool _ CacheLinePad } var MIPS64X struct { _ CacheLinePad HasMSA bool // MIPS SIMD architecture _ CacheLinePad } // For ppc64(le), it is safe to check only for ISA level starting on ISA v3.00, // since there are no optional categories. There are some exceptions that also
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 19:57:43 UTC 2024 - 7.1K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arm64.go
a.Index = num case "D": if !isIndex { return nil } a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_D & 15) << 5) a.Index = num default: return errors.New("unsupported simd register extension type: " + ext) } } else { return errors.New("invalid register and extension combination") } return nil }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Sep 29 09:04:58 UTC 2022 - 10.4K bytes - Viewed (0) -
go.mod
github.com/minio/colorjson v1.0.8 // indirect github.com/minio/filepath v1.0.0 // indirect github.com/minio/mc v0.0.0-20240612143403-e7c9a733c680 // indirect github.com/minio/md5-simd v1.1.2 // indirect github.com/minio/pkg/v2 v2.0.19 // indirect github.com/minio/websocket v1.6.0 // indirect github.com/mitchellh/mapstructure v1.5.0 // indirect
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Thu Jun 13 22:53:53 UTC 2024 - 11.5K bytes - Viewed (0) -
internal/s3select/select.go
} buf.WriteString(s3Select.Output.CSVArgs.RecordDelimiter) return nil case jsonFormat: err := record.WriteJSON(buf) if err != nil { return err } // Trim trailing newline from non-simd output if buf.Bytes()[buf.Len()-1] == '\n' { buf.Truncate(buf.Len() - 1) } buf.WriteString(s3Select.Output.JSONArgs.RecordDelimiter) return nil }
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Fri May 24 23:05:23 UTC 2024 - 21K bytes - Viewed (0) -
src/math/big/arith_arm64.s
//go:build !math_big_pure_go #include "textflag.h" // This file provides fast assembly versions for the elementary // arithmetic operations on vectors implemented in arith.go. // TODO: Consider re-implementing using Advanced SIMD // once the assembler supports those instructions. // func addVV(z, x, y []Word) (c Word) TEXT ·addVV(SB),NOSPLIT,$0 MOVD z_len+8(FP), R0 MOVD x+24(FP), R8 MOVD y+48(FP), R9 MOVD z+0(FP), R10
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 11.8K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/plan9x.go
if regenum >= uint16(B0) && regenum <= uint16(Q31) { if strings.HasPrefix(inst.Op.String(), "F") || strings.HasSuffix(inst.Op.String(), "CVTF") || fOpsWithoutFPrefix[inst.Op] { // FP registers are the same ones as SIMD registers // Print Fn for scalar variant to align with assembler (e.g., FCVT, SCVTF, UCVTF, etc.) return fmt.Sprintf("F%d", regno) } else { // Print Vn to align with assembler (e.g., SHA256H)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 16 22:24:28 UTC 2022 - 17K bytes - Viewed (0) -
go.sum
github.com/minio/mc v0.0.0-20240612143403-e7c9a733c680/go.mod h1:21/cb+wUd+lLRsdX7ACqyO8DzPNSpXftp1bOkQlIbh8= github.com/minio/md5-simd v1.1.2 h1:Gdi1DZK69+ZVMoNHRXJyNcxrMA4dSxoYHZSQbirFg34= github.com/minio/md5-simd v1.1.2/go.mod h1:MzdKDxYpY2BT9XQFocsiZf/NKVtR7nkE4RoEpN+20RM= github.com/minio/minio-go/v6 v6.0.46/go.mod h1:qD0lajrGW49lKZLtXKtCB4X/qkMf0a5tBvN2PaZg7Gg=
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Thu Jun 13 22:53:53 UTC 2024 - 85.8K bytes - Viewed (0) -
src/cmd/internal/obj/link.go
// Encoding: // type = TYPE_REG // reg = REG_[US]XT[BHWX] + register + shift amount // offset = ((reg&31) << 16) | (exttype << 13) | (amount<<10) // // reg.<T> // Register arrangement for ARM64 SIMD register // e.g.: V1.S4, V2.S2, V7.D2, V2.H4, V6.B16 // Encoding: // type = TYPE_REG // reg = REG_ARNG + register + arrangement // // reg.<T>[index] // Register element for ARM64 // Encoding:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 19:57:43 UTC 2024 - 33.1K bytes - Viewed (0) -
internal/s3select/select_test.go
if !reflect.DeepEqual(gotS, testCase.wantResult) { t.Errorf("received response does not match with expected reply. Query: %s\ngot: %s\nwant:%s", testCase.query, gotS, testCase.wantResult) } }) t.Run("simd-"+testCase.name, func(t *testing.T) { if !simdjson.SupportedCPU() { t.Skip("No CPU support") } testReq := testCase.requestXML if len(testReq) == 0 { var escaped bytes.Buffer
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Sat Dec 23 07:19:11 UTC 2023 - 76.2K bytes - Viewed (0)