GOARM64
		For GOARCH=arm64, the ARM64 architecture for which to compile.
		Valid values are v8.0 (default), v8.{1-9}, v9.{0-5}.
		The value can be followed by an option specifying extensions implemented by target hardware.
		Valid options are ,lse and ,crypto.
		Note that some extensions are enabled by default starting from a certain GOARM64 version;
		for example, lse is enabled by default starting from v8.1.
	GO386

	aCache |= uint64(bytes[7]) << (7 * 8)
	s.allocCache = ^aCache
}

// nextFreeIndex returns the index of the next free object in s at
// or after s.freeindex.
// There are hardware instructions that can be used to make this
// faster if profiling warrants it.
func (s *mspan) nextFreeIndex() uint16 {
	sfreeindex := s.freeindex
	snelems := s.nelems
	if sfreeindex == snelems {

	// runtime detection of CPU manufacturer.
	MFENCE
	LFENCE
	RDTSC
	JMP done

// func memhash(p unsafe.Pointer, h, s uintptr) uintptr
// hash function using AES hardware instructions
TEXT runtime·memhash<ABIInternal>(SB),NOSPLIT,$0-32
	// AX = ptr to data
	// BX = seed
	// CX = size
	CMPB	runtime·useAeshash(SB), $0
	JEQ	noaes
	JMP	aeshashbody<>(SB)
noaes:

)

const (
	// R bit option in prefixed load/store/add D-form operations
	PFX_R_ABS   = 0 // Offset is absolute
	PFX_R_PCREL = 1 // Offset is relative to PC, RA should be 0
)

const (
	// The preferred hardware nop instruction.
	NOP = 0x60000000
)

type Optab struct {
	as    obj.As // Opcode
	a1    uint8  // p.From argument (obj.Addr). p is of type obj.Prog.
	a2    uint8  // p.Reg argument (int16 Register)

    deps = [
        ":execution_metadata_exporter",
        ":runtime_metadata_fbs",
        "//tensorflow/compiler/mlir/lite:tensorflow_lite",
        "//tensorflow/compiler/mlir/lite/experimental/tac/hardwares:all-target-hardwares",
        "@com_google_googletest//:gtest_main",
        "@flatbuffers",
        "@llvm-project//mlir:ArithDialect",
        "@llvm-project//mlir:FuncDialect",
        "@llvm-project//mlir:IR",

			if goarch == "arm64" {
				for i := range symtab {
					if symtab[i].Name == "__hwasan_init" {
						// -fsanitize=hwaddress on ARM
						// uses the upper byte of a
						// memory address as a hardware
						// tag. Remove it so that
						// we can find the associated
						// data.
						removeTag = func(v uint64) uint64 { return v &^ (0xff << (64 - 8)) }
						break
					}
				}
			}

(AndB ...) => (AND ...)
(OrB  ...) => (OR ...)
(EqB  x y) => (XOR (MOVDconst [1]) (XOR <typ.Bool> x y))
(NeqB ...) => (XOR ...)
(Not    x) => (XOR (MOVDconst [1]) x)

// shifts
// hardware instruction uses only the low 6 bits of the shift
// we compare to 64 to ensure Go semantics for large shifts
// Rules about rotates with non-const shift are based on the following rules,

//	GOARM64
//		For GOARCH=arm64, the ARM64 architecture for which to compile.
//		Valid values are v8.0 (default), v8.{1-9}, v9.{0-5}.
//		The value can be followed by an option specifying extensions implemented by target hardware.
//		Valid options are ,lse and ,crypto.
//		Note that some extensions are enabled by default starting from a certain GOARM64 version;
//		for example, lse is enabled by default starting from v8.1.
//	GO386

    `[b, f, 0, 1]x[o, i, 0, 1]->[b, f, 0, 1]` format and converts it to
    `[b, 0, 1, f]x[0, 1, i, o]->[b, 0, 1, f]` format.

    This pass is useful to convert models that conventionally use the NCHW
    format to target hardwares that are more NHWC-friendly.
  }];
  let dependentDialects = ["mlir::stablehlo::StablehloDialect"];
}

def DeferActivationTransposePass : Pass<"stablehlo-defer-activation-transpose", "mlir::func::FuncOp"> {

//
// Design doc at https://golang.org/s/go11sched.

// Worker thread parking/unparking.
// We need to balance between keeping enough running worker threads to utilize
// available hardware parallelism and parking excessive running worker threads
// to conserve CPU resources and power. This is not simple for two reasons:
// (1) scheduler state is intentionally distributed (in particular, per-P work