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Results 21 - 22 of 22 for SUBW (0.06 sec)
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src/cmd/compile/internal/ssa/rewriteRISCV64.go
v_1 := v.Args[1] v_0 := v.Args[0] // match: (SUBW x (MOVDconst [0])) // result: (ADDIW [0] x) for { x := v_0 if v_1.Op != OpRISCV64MOVDconst || auxIntToInt64(v_1.AuxInt) != 0 { break } v.reset(OpRISCV64ADDIW) v.AuxInt = int64ToAuxInt(0) v.AddArg(x) return true } // match: (SUBW (MOVDconst [0]) x) // result: (NEGW x) for {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 205.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, outputs: []outputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, }, }, { name: "SUBW", argLen: 2, asm: riscv.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)