if (input_batch != ShapedType::kDynamic &&
        input_batch % (block_size * block_size) != 0) {
      return op.emitOpError()
             << "requires input batch (dimension 0) to be evenly divisible "
                "by (block_size * block_size), but got input batch "
             << input_batch << " and block_size " << block_size;
    }

    input_shape.assign(input_type.getShape().begin(),

		}
	}
	if pagesPerArena%pagesPerSpanRoot != 0 {
		print("pagesPerArena (", pagesPerArena, ") is not divisible by pagesPerSpanRoot (", pagesPerSpanRoot, ")\n")
		throw("bad pagesPerSpanRoot")
	}
	if pagesPerArena%pagesPerReclaimerChunk != 0 {
		print("pagesPerArena (", pagesPerArena, ") is not divisible by pagesPerReclaimerChunk (", pagesPerReclaimerChunk, ")\n")
		throw("bad pagesPerReclaimerChunk")
	}

    return
  }

  // Test that map_outside_compilation's inputs shapes are divisible by num_cores_per_replica.
  func.func @map_outside_compilation_div_num_cores_per_replica() -> () {
    "tf_device.cluster"() ({
      %0 = "tf.OpA"() : () -> tensor<3xi64>
      // expected-error @+1 {{divisible by num_cores_per_replica}}

  if (in_shape[0] % num_cores_per_replica != 0) {
    return context_op->emitOpError()
           << "A map_outside_compilation op's input and output shapes must be "
              "divisible by num_cores_per_replica="
           << num_cores_per_replica;
  }
  llvm::SmallVector<int64_t, 4> shape;
  shape.push_back(split_size);
  for (int i = 1; i < in_shape.size(); ++i) {

                            << kernel_output_features << ") to be divisible by "
                            << "feature_group_count (value "
                            << feature_group_count_val << ").\n";
  }
  if (input_batch % batch_group_count != 0) {
    return op.emitOpError()
           << "Expected input batch dimension (value " << input_batch
           << " ) to be divisible by batch_group_count (value "

}

// -----

func.func @testConv2D(%arg0: tensor<256x32x32x3xf32>, %arg1: tensor<3x3x2x16xf32>) -> tensor<256x32x32x16xf32> {
  // expected-error @+1 {{requires the number of input channels to be divisible by the number of filter input channels; found 3 and 2, respectively}}
  %0 = "tf.Conv2D"(%arg0, %arg1) {padding = "SAME", strides = [1, 1, 1, 1]} : (tensor<256x32x32x3xf32>, tensor<3x3x2x16xf32>) -> tensor<256x32x32x16xf32>

    // all spatial dimensions.
    const int64_t filter_channels = GetDimSize(filter_ty, num_spatial_dims);
    // TensorFlow convolution op verifies that the number of input channels is
    // divisible by the number of filter channels.
    // For depthwise convolution the feature_group_count argument would be set
    // to the input feature dimension.
    const int64_t feature_group_count =

  if (op.getNumResults() == 0) return failure();

  if (input_dim_size % op.getNumResults() != 0)
    return op.emitOpError("dimension #")
           << *dim_index << " not divisible by the number of result tensors";

  return success();
}

//===----------------------------------------------------------------------===//
// SplitVOp

    // expected-error@+1 {{incorrect input sharding configuration received. 1-th dimension of the input must be evenly divisible by 4}}

    %strides = "tf.Const"() {value = dense<[3, 1, 1]> : tensor<3xi32>} : () -> tensor<3xi32>
    // expected-error @below {{'tf.XlaConvV2' op Expected output feature dimension (value 9) to be divisible by feature_group_count (value 2).}}