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Results 21 - 30 of 147 for cond_a (0.19 sec)
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cmd/postpolicyform.go
} case []interface{}: // Handle array types. if len(condt) != 3 { // Return error if we have insufficient elements. return parsedPolicy, fmt.Errorf("Malformed conditional fields %s of type %s found in POST policy form", condt, reflect.TypeOf(condt).String()) } switch toLowerString(condt[0]) { case policyCondEqual, policyCondStartsWith: for _, v := range condt { // Pre-check all values for type. if !isString(v) {
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Mon May 06 10:52:41 UTC 2024 - 12.3K bytes - Viewed (0) -
guava-tests/test/com/google/common/base/EnumsTest.java
@J2ktIncompatible public class EnumsTest extends TestCase { private enum TestEnum { CHEETO, HONDA, POODLE, } public void testGetIfPresent() { assertThat(Enums.getIfPresent(TestEnum.class, "CHEETO")).hasValue(TestEnum.CHEETO); assertThat(Enums.getIfPresent(TestEnum.class, "HONDA")).hasValue(TestEnum.HONDA); assertThat(Enums.getIfPresent(TestEnum.class, "POODLE")).hasValue(TestEnum.POODLE);
Registered: Wed Jun 12 16:38:11 UTC 2024 - Last Modified: Wed May 29 16:29:37 UTC 2024 - 8.7K bytes - Viewed (0) -
tensorflow/compiler/mlir/tfrt/tests/tf_to_corert/merge_tf_if_ops.mlir
} func.func @nested_if_op_then_0(%cond: tensor<i1>, %x: tensor<i32>, %y: tensor<i32>) -> (tensor<i32>, tensor<i32>) { %0 = "tf.AddV2"(%x, %y) : (tensor<i32>, tensor<i32>) -> tensor<i32> func.return %0, %0 : tensor<i32>, tensor<i32> } func.func @nested_if_op_else_0(%cond: tensor<i1>, %x: tensor<i32>, %y: tensor<i32>) -> (tensor<i32>, tensor<i32>) {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 8.4K bytes - Viewed (0) -
tensorflow/compiler/mlir/tfrt/tests/mlrt/inline.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri Mar 22 01:01:31 UTC 2024 - 2.3K bytes - Viewed (0) -
istioctl/pkg/writer/envoy/configdump/listener.go
} func describeMatch(match *route.RouteMatch) string { conds := []string{} if match.GetPrefix() != "" { conds = append(conds, fmt.Sprintf("%s*", match.GetPrefix())) } if match.GetPathSeparatedPrefix() != "" { conds = append(conds, fmt.Sprintf("PathPrefix:%s", match.GetPathSeparatedPrefix())) } if match.GetPath() != "" { conds = append(conds, match.GetPath()) } if match.GetSafeRegex() != nil {
Registered: Fri Jun 14 15:00:06 UTC 2024 - Last Modified: Wed Nov 29 12:37:14 UTC 2023 - 18.1K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/ir/tf_ops_n_z.cc
// operation: // // * Operands and cond inputs to call the cond function before the // first iteration. // * Operands and body inputs to call the body function for the first // iteration if the cond functions returns True or equivalent result. // * Operands and results to assign cond function arguments to op results if // the cond function returns False or equivalent result. If the op is shape
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 09 22:07:10 UTC 2024 - 170.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteAMD64latelower.go
v_0 := v.Args[0] // match: (MOVBQZX x) // cond: zeroUpper56Bits(x,3) // result: x for { x := v_0 if !(zeroUpper56Bits(x, 3)) { break } v.copyOf(x) return true } return false } func rewriteValueAMD64latelower_OpAMD64MOVLQZX(v *Value) bool { v_0 := v.Args[0] // match: (MOVLQZX x) // cond: zeroUpper32Bits(x,3) // result: x for { x := v_0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 3.6K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/transforms/tensor_list_ops_decomposition.cc
// Rewrite cond. auto cond = while_op.cond_function(); llvm::SmallDenseMap<Value, SizeInfo> cond_map; ModifyFunctionSignature(cond, cutil::GetSizeType(builder), &cond_map, find_arg_tensor_list_type, arg_buffer_size_is_fixed); if (failed(DecomposeTensorListOpsInternal( &cond.front(), module, &cond_map, decomposed_partitioned_call_callees))) {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Apr 25 16:01:03 UTC 2024 - 39.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteAMD64.go
v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] // match: (CMOVLCC x y (InvertFlags cond)) // result: (CMOVLLS x y cond) for { x := v_0 y := v_1 if v_2.Op != OpAMD64InvertFlags { break } cond := v_2.Args[0] v.reset(OpAMD64CMOVLLS) v.AddArg3(x, y, cond) return true } // match: (CMOVLCC _ x (FlagEQ)) // result: x for { x := v_1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 712.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteRISCV64.go
case BlockRISCV64BEQ: // match: (BEQ (MOVDconst [0]) cond yes no) // result: (BEQZ cond yes no) for b.Controls[0].Op == OpRISCV64MOVDconst { v_0 := b.Controls[0] if auxIntToInt64(v_0.AuxInt) != 0 { break } cond := b.Controls[1] b.resetWithControl(BlockRISCV64BEQZ, cond) return true } // match: (BEQ cond (MOVDconst [0]) yes no) // result: (BEQZ cond yes no)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 205.1K bytes - Viewed (0)